Patent application number | Description | Published |
20080277779 | Microelectronic package and method of manufacturing same - A microelectronic package comprises a substrate ( | 11-13-2008 |
20090034206 | WAFER-LEVEL ASSEMBLY OF HEAT SPREADERS FOR DUAL IHS PACKAGES - An embodiment of the present invention is a technique to fabricate a package. A heat spreader (HS) array on a HS support substrate is formed. The HS array has a plurality of heat spreaders. A diced wafer supported by a wafer support substrate (WSS) is formed. The diced wafer has a plurality of thin dice. The thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS. | 02-05-2009 |
20090166852 | SEMICONDUCTOR PACKAGES WITH THERMAL INTERFACE MATERIALS - A method comprises providing a layer of nano particles between a semiconductor die and a slug; and sintering the layer of nano particles to provide thermal interface material to bond the semiconductor die to a heat spreader formed by the slug. The sintering temperature of the nano particles is around 50° C. to around 200° C. | 07-02-2009 |
20100320576 | Die-warpage compensation structures for thinned-die devices, and methods of assembling same - A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die. | 12-23-2010 |
20110147059 | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same - Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed. | 06-23-2011 |
20110147440 | Solder in Cavity Interconnection Technology - An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball. | 06-23-2011 |
20120241965 | SOLDER IN CAVITY INTERCONNECTION STRUCTURES - The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate. | 09-27-2012 |
20130206820 | SOLDER IN CAVITY INTERCONNECTION TECHNOLOGY - An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball. | 08-15-2013 |
20130343022 | SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP - In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board. | 12-26-2013 |
20130344659 | MICROELECTRONIC PACKAGE HAVING DIRECT CONTACT HEAT SPREADER AND METHOD OF MANUFACTURING SAME - A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die. | 12-26-2013 |
20140001629 | PACKAGED SEMICONDUCTOR DIE AND CTE-ENGINEERING DIE PAIR | 01-02-2014 |
20140035134 | DENSE INTERCONNECT WITH SOLDER CAP (DISC) FORMATION WITH LASER ABLATION AND RESULTING SEMICONDUCTOR STRUCTURES AND PACKAGES - Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method of fabricating a semiconductor structure includes forming an insulative material stack above a plurality of solder bump landing pads. The solder bump landing pads are above an active side of a semiconductor die. A plurality of trenches is formed in the insulative material stack by laser ablation to expose a corresponding portion of each of the plurality of solder bump landing pads. A solder bump is formed in each of the plurality of trenches. A portion of the insulative material stack is then removed. | 02-06-2014 |
20140048959 | MICROELECTRONIC PACKAGE HAVING NON-COPLANAR, ENCAPSULATED MICROELECTRONIC DEVICES AND A BUMPLESS BUILD-UP LAYER - A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar), The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate. | 02-20-2014 |
20140061954 | SEMICONDUCTOR DEVICE WITH PRE-MOLDING CHIP BONDING - This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact. | 03-06-2014 |
20140063761 | OFF-PLANE CONDUCTIVE LINE INTERCONNECTS IN MICROELECTRONIC DEVICES - Off-plane conductive line interconnects may be formed in microelectronic devices. In one example, such as device includes a first set of metal conductive lines in a dielectric substrate at a first horizontal layer of the substrate, a second set of metal conductive lines in the substrate at the first horizontal layer of the substrate and vertically offset from the first set of metal lines, and a dielectric material insulating the metal lines from each other and the first horizontal layer from other horizontal layers. Vias in the dielectric material to connect both the first and second set of metal lines to metal lines at a second horizontal layer of the substrate. | 03-06-2014 |
20140167217 | PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER - Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed. | 06-19-2014 |
20140240943 | SOLDER IN CAVITY INTERCONNECTION TECHNOLOGY - An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball. | 08-28-2014 |
20140293529 | Method Apparatus and Material for Radio Frequency Passives and Antennas - A method apparatus and material are described for radio frequency passives and antennas. In one example, an electronic component has a synthesized magnetic nanocomposite material with aligned magnetic domains, a conductor embedded within the nanocomposite material, and contact pads extending through the nanocomposite material to connect to the conductor. | 10-02-2014 |
20140299999 | INTEGRATED CIRCUIT PACKAGE ASSEMBLIES INCLUDING A GLASS SOLDER MASK LAYER - Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. Other embodiments may be described and/or claimed. | 10-09-2014 |
20150008595 | SEMICONDUCTOR DEVICE WITH PRE-MOLDING CHIP BONDING - This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact. | 01-08-2015 |
20150187727 | SOLDER IN CAVITY INTERCONNECTION STRUCTURES - The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate. | 07-02-2015 |
20150279824 | ELECTRONIC PACKAGE AND METHOD OF FORMING AN ELECTRONIC PACKAGE - An electronic package that includes a mold that includes at least one passive component, each of the passive components including electric conductors that are exposed from the mold, and a first conductive layer directly attached to the mold such that the conductive layer touches the mold and the electrical conductors that are exposed from the mold. A method that includes removing a temporary carrier from a mold that includes electronic devices, wherein electric conductors on the electronic devices are exposed once the temporary carrier is removed from the mold, and covering the mold with a first conductive layer such that the first conductive layer covers the mold and is electrically connected to the exposed electric conductors on the electronic devices. | 10-01-2015 |
20150282341 | ELECTRIC CIRCUIT ON FLEXIBLE SUBSTRATE - Generally discussed herein are systems and apparatuses that can include a flexible substrate with a hermetic seal formed thereon. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a hermetic seal on a flexible substrate can include (1) forming an interconnect on a flexible substrate, (2) situating a device on the substrate near the interconnect, or (3) selectively depositing a first hermetic material on the device or interconnect so as to hermetically seal the device within the combination of the interconnect and first hermetic material. | 10-01-2015 |
Patent application number | Description | Published |
20090214475 | Extractability and Bioavailability of the Natural Antioxidant Astaxanthin From a Green Alga, Haematococcus Pluvialis - As the richest source of astaxanthin, a natural antioxidant and coloring agent, the unicellular green alga, | 08-27-2009 |
20100021968 | NOVEL CHLORELLA SPECIES AND USES THEREFOR - The present invention relates to algal species and compositions, methods for identifying algae that produce high lipid content, possess tolerance to high CO | 01-28-2010 |
20100028962 | Algal Medium Chain Length Fatty Acids and Hydrocarbons - The present invention provides methods and compositions for production of algal-based medium chain fatty acids and hydrocarbons. | 02-04-2010 |
20100028976 | PHOTOBIOREACTOR AND USES THEREFOR - The present invention provides novel photobioreactors, modules thereof, and methods for use in culturing and harvesting algae and cyanobacteria. | 02-04-2010 |
20100255541 | Advanced Algal Photosynthesis-Driven Bioremediation Coupled with Renewable Biomass and Bioenergy Production - The present invention relates to algal species and compositions, methods for identifying algae that produce high lipid content, possess tolerance to high CO | 10-07-2010 |
20100267085 | NOVEL PSEUDOCHLOROCOCCUM SPECIES AND USES THEREFOR - The present invention relates to algal species and compositions, methods for identifying algae that produce high lipid content and possess CO | 10-21-2010 |
20110253605 | ALGAE FILTRATION SYSTEMS AND METHODS - Systems and methods for filtering algae from fluid including a piston and pressurized air system to scrape and clean algae from the filter. | 10-20-2011 |
20110253612 | Extraction With Fractionation of Oil and Co-Products From Oleaginous Material - Systems and methods for extracting lipids of varying polarities from oleaginous material. | 10-20-2011 |
20110253646 | ALGAE FILTRATION SYSTEMS AND METHODS - Systems and methods for filtering algae from fluid including a piston and pressurized air system to scrape and clean algae from the filter. | 10-20-2011 |
20110263883 | Extraction With Fractionation of Oil and Co-Products from Oleaginous Material - Systems and methods for extracting lipids of varying polarities from oleaginous material. | 10-27-2011 |
20120031858 | ALGAE HARVESTING DEVICES AND METHODS - Systems and methods for filtering and collecting algae from fluid including a piston and pressurized air system to scrape and clean algae from the filter. | 02-09-2012 |
20120034662 | CO-CULTURING ALGAL STRAINS TO PRODUCE FATTY ACIDS OR HYDROCARBONS - The present invention provides methods and compositions for production of algal-based medium chain fatty acids and hydrocarbons. | 02-09-2012 |
20120065418 | Extraction of lipids from oleaginous material - Systems and methods for extracting lipids of varying polarities from oleaginous material. | 03-15-2012 |
20120070869 | Methods of using Nannochloropsis Algal strains to produce hydrocarbons and fatty acids - The present invention provides methods and compositions for production of algal-based medium chain fatty acids and hydrocarbons. More specifically, the invention relates to a | 03-22-2012 |
20120085694 | ALGAE HARVESTING DEVICES - Systems and methods for filtering and collecting algae from fluid including a piston and pressurized air system to scrape and clean algae from the filter. | 04-12-2012 |
20120094361 | Method of Separation of Algal Biomass from Aqueous or Marine Culture - Disclosed are cross-flow membrane filtration methods for the removal or separation of algal cells from an aqueous environment. The methods of the invention may be used for the simultaneous algal harvesting/dewatering and water/wastewater purification and recycling. | 04-19-2012 |
20120107918 | METHODS OF ALGAL GROWTH IN PHOTOBIOREACTORS - The present invention provides novel photobioreactors, modules thereof, and methods for use in culturing and harvesting algae and cyanobacteria. | 05-03-2012 |
20120135478 | ALGAL MEDIUM CHAIN LENGTH FATTY ACIDS AND HYDROCARBONS - The present invention provides methods and compositions for production of algal-based medium chain fatty acids and hydrocarbons. More specifically, the invention relates to a | 05-31-2012 |
20120264958 | Extraction with Fractionation of Lipids and Co-Products From Oleaginous Material - Systems and methods for extracting lipids of varying polarities from oleaginous material. | 10-18-2012 |
20120315692 | Photobioreactor And Uses Therefor - The present invention provides novel photobioreactors, modules thereof, and methods for use in culturing and harvesting algae and cyanobacteria. | 12-13-2012 |
20130041168 | EXTRACTION WITH FRACTIONATION OF LIPIDS AND PROTEINS FROM OLEAGINOUS MATERIAL - Systems and methods for extracting lipids of varying polarities from oleaginous material. | 02-14-2013 |
20150322468 | METHOD OF PRODUCING BIOFUEL USING MICROALGAE CULTURES - The present invention relates to methods of improving TAG production of microalgae, for example, the microalgae in microalgal mass culture systems, and compositions of the improved microalgae. The method of improving TAG production may be increasing the yield of TAG produced by each microalgae or increasing the total yield of a mass culture system by increasing the number of microalgae in the mass culture system. | 11-12-2015 |