Patent application number | Description | Published |
20090278574 | Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider - A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal. | 11-12-2009 |
20090278579 | Delay Line Calibration Mechanism and Related Multi-Clock Signal Generator - A delay line calibration mechanism includes a delay line, a phase detector, and a controller. The delay line receives an input pulse, a calibration pulse, a first delay selection signal, and a second delay selection signal, delays the input pulse for a delay period according to the first delay selection signal to output a delayed pulse, and delays the calibration pulse for a calibration delay period according to the second delay selection signal to output a delayed calibration pulse. The controller is for generating the input pulse, the calibration pulse, and a reference pulse. The controller also generates the first delay selection signal, and generates the second delay selection signal according to a phase difference signal. The phase detector is for generating the phase difference signal indicating the difference between the delayed calibration pulse and the reference pulse by comparing the delayed calibration pulse and the reference pulse. | 11-12-2009 |
20090289674 | PHASE-LOCKED LOOP - A phase-locked loop includes a phase detector, a charge pump and a controllable oscillator. The phase detector is supplied by a first supply voltage and is utilized for comparing a phase difference between an reference input signal and a feedback signal based on an output signal to generate at least one detect signal. The charge pump is supplied by a second supply voltage, and is utilized for generating a control signal with charge amounts according to the detect signal, where the first supply voltage is different from the second supply voltage. The controllable oscillator is utilized for generating the output signal according to the control signal, wherein a frequency of the output signal is adjusted by the control signal. | 11-26-2009 |
20110089985 | Delay Line Calibration Mechanism and Related Multi-Clock Signal Generator - A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the first delay selection signal to output a first delayed pulse. The second delay line receives a second pulse and a second delay selection signal, and delays the second pulse for a second delay period according to the second delay selection signal to output a second delayed pulse. The phase detector generates a phase difference signal indicating the phase difference between the first delayed pulse and the second delayed pulse by comparing the first delayed pulse and the second delayed pulse. The controller generates the second delay selection signal, and generates the first delay selection signal according to the phase difference signal. | 04-21-2011 |
20110254606 | Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider - A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal. | 10-20-2011 |
20150022259 | CALIBRATION METHOD AND APPARATUS FOR CURRENT AND RESISTANCE - A calibration method and apparatus for current and resistance are provided, where the current calibration method includes: injecting at least one portion of a set of predetermined compensation currents into at least one of an output current of a first current source and an output current of a second current source, and dynamically adjusting a distribution of the at least one portion of the set of predetermined compensation currents until two monitored voltage drops are equal to each other, and recording a first compensation current configuration; exchanging the first and second current sources, and dynamically adjusting the distribution of the at least one portion of the set of predetermined compensation currents until the two monitored voltage drops are equal to each other, and recording a second compensation current configuration; and according to the first and second compensation current configurations, generating a resultant compensation current, for use of current compensation. | 01-22-2015 |
Patent application number | Description | Published |
20080198648 | WRITING METHOD FOR MAGNETIC MEMORY CELL AND MAGNETIC MEMORY ARRAY STRUCTURE - A writing method for a magnetic memory cell which has a magnetic free stack layer with a bi-directional easy axis. A magnetic X axis and a magnetic Y axis are taken as reference directions, and the bi-directional easy axis is substantially on the magnetic X axis. The method includes applying a first magnetic field in a first direction of the magnetic Y axis. Then, a second magnetic field added onto the first magnetic field is applied in a first direction of the magnetic X axis. Next, the application of the first magnetic field is terminated. Thereafter, a third magnetic field is applied on the magnetic Y axis in a second direction opposite to the first direction. The second magnetic field is terminated and the third magnetic field is terminated. | 08-21-2008 |
20080298119 | MAGNETIC MEMORY CELL WITH MULTIPLE-BIT IN STACKED STRUCRUTE AND MAGNETIC MEMORY DEVICE - A multi-bit magnetic memory cell in a stacked structure controlled by at least one read bit line and one read word line is provided. The multi-bit magnetic memory cell includes at least two magnetic memory units and a switching device. Each magnetic memory unit has a magneto-resistance value and at least the two magnetic memory units are stacked to form a circuit of serial connection or parallel connection. The circuit and the read bit line are connected. The switching device is connected to the circuit, wherein the switching device is controlled by the read word line to be conducting or non-conducting so as to connect the circuit with a ground voltage. Furthermore, a plurality of the multi-bit magnetic cells is used to form a magnetic memory device. | 12-04-2008 |
20090034322 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATION METHOD - A magnetic random access memory includes at least a first-direction write current line and multiple second-direction write current line, intersecting with the first-direction write current line in substantial perpendicular and forming several intersecting regions. Multiple magnetic memory cells are respectively located at the intersecting regions for receiving an induced magnetic field in a time sequence. Every at least two adjacent memory cells are in parallel or series connection, to form at least one memory unit. An easy axis of a free layer of each magnetic memory cell is substantially perpendicular to a magnetization of a pinned layer. The easy axis and the first-direction write current line form an including angle of about 45°. A read bit-line circuit connects to a first terminal of the memory unit. A read word-line circuit connects to a second terminal of the memory unit. | 02-05-2009 |
Patent application number | Description | Published |
20110199336 | OPTICAL TOUCH DEVICE - An optical touch device is presented. When the optical touch device is in a sleep mode, only one of all image sensors of the optical touch device is enabled to detect an indication object on a touch area, so as to determine a wakeup time of the entire optical touch device. | 08-18-2011 |
20120249293 | RECOGNITION SYSTEM AND RECOGNITION METHOD - A recognition system is used for recognizing an operation of a user. The recognition system includes a sensor module, a processing device, a playing device, and data storage device. The sensor module is used for generating a first sensing signal according to an operation of a user. The data storage device stores a plurality of objects. The processing device compares the first sensing signal with the plurality of objects to generate a recognition result in response to the first sensing signal. The playing device is used for playing the recognition result. The sensor module is used for, after the recognition result is played, recognizing a response of the user to generate a second sensing signal, and feeding the second sensing signal back to the processing device. The processing device judges whether the recognition result corresponding to the first sensing signal is correct according to the second sensing signal. | 10-04-2012 |
20130300351 | WIRELESS TRANSCEIVER AND WIRELESS TRANSCEIVER SYSTEM - A wireless transceiver coupled to a human interface device (HID) having a first coil is provided. The wireless transceiver includes a control module, a port, and a second coil. The control module includes a radio frequency (RF) unit, a conversion unit, and an electricity power unit. The RF unit is used to receive a RF signal outputted from the HID. | 11-14-2013 |
20130300663 | POWER-SAVING SENSING MODULE FOR OPTICAL MOUSE AND POWER-SAVING SENSING METHOD - A power-saving sensing module includes a light source, a first and a second sensor, a first and a second detection unit, and a controller. The first sensor detects a first image corresponding to a working plane in response to at least a part of the light ray from the light source to generate a first sensing signal. The first detection unit generates a displacement signal in response to the first sensing signal. The second sensor detects a second image corresponding to an object in response to at least a part of light ray to generate a second sensing signal. The second detection unit generates a touch signal corresponding to the object in response to the second sensing signal. The controller outputs a control signal in response to the touch signal. The first detection unit operates at a dormant state or a sensing state in response to the control signal. | 11-14-2013 |
20130300713 | POWER-SAVING SENSING MODULE AND METHOD THEREOF - A power-saving sensing module includes a light source, a first and a second sensor, a first and a second detection unit, and a controller. The first sensor detects a touch of an external object to generate a first sensing signal corresponding to the touch. The first detection unit generates a touch signal corresponding to the first sensing signal. | 11-14-2013 |
Patent application number | Description | Published |
20110296365 | EXTRACTING METHODS FOR CIRCUIT MODELS - The present invention relates to an extracting method for a circuit model, configured to represent output driving capability and an input capacitor of an interface pin of an application circuit. The extracting method comprises: receiving a netlist describing a circuit structure of the application circuit, which comprises a plurality of transistors; selecting an interface pin of the application circuit in the netlist; selecting a bias pin of the application circuit in the netlist; selecting at least one path between the interface pin and the bias pin in the netlist; and obtaining sum of equivalent width/length ratios according to the width/length ratios of all first transistors coupled to the at least one path. | 12-01-2011 |
20130185683 | Method of Generating Integrated Circuit Model - An integrated circuit test model is generated according to a circuit connection net-list, an isolation cell topology, and a pin voltage information spec file, so that the procedure of generating the integrated circuit test model can be time-saving, efficient, and fool-proof. Besides, while tracing a current path of a node of the circuit connection net-list, the generated integrated circuit test model can be more precise if certain limitations are added. | 07-18-2013 |
20130298095 | METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM - A computer readable medium includes a program code for checking whether an I/O cell of a chip design has a connection error or not, where the chip design includes a plurality of I/O cells and a plurality of blocks, and when the program code is executed by a processor, the program code executes following steps: checking a connection between the I/O cell and a block by utilizing a check item corresponding to an attribute of the I/O cell to generate a checking result; and determining whether the I/O cell has a connection error according to the checking result. | 11-07-2013 |
20140223398 | METHOD FOR DETERMINING INTERFACE TIMING OF INTEGRATED CIRCUIT AUTOMATICALLY AND RELATED MACHINE READABLE MEDIUM THEREOF - A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file. | 08-07-2014 |
20150067623 | TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM - A timing analysis method applied for a non-standard cell circuit, includes: identifying at least a first register and a second register from the circuit; calculating at least one path delay of at least one path between the first register and the second register; calculating a first register clock delay from a first clock source to a first register clock input terminal of the first register; calculating a second register clock delay from a second clock source to a second register clock input terminal of the second register; and determining whether timing violation takes place in respect of the second register according to the path delay, the first register clock delay, the second register clock delay, and a first register delay of the first register. | 03-05-2015 |
Patent application number | Description | Published |
20110116652 | SIGNAL OUTPUT DEVICE AND SIGNAL OUTPUT METHOD - A signal output device includes: a control circuit for receiving at least a first input control signal and outputting an output control signal according to at least the first input control signal, wherein the first input control signal comprises a first signal segment followed by a second signal segment; and a driver circuit, operated according to a supply power, for receiving the output control signal from the control circuit and selectively generating an output signal according to the output control signal; wherein the supply power is turned on before the second signal segment of the first input control signal is received by the control circuit; when the supply power is turned on, the driver circuit operates under a specific power state; and when the second signal segment of the first input control signal is received by the control circuit, the driver circuit keeps operating under the specific power state. | 05-19-2011 |
20130099839 | SEGMENTED FRACTIONAL-N PLL - A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing. | 04-25-2013 |
20150131811 | SIGNAL OUTPUT DEVICE AND SIGNAL OUTPUT METHOD - A signal output device includes: a control circuit for receiving at least a first input control signal and outputting an output control signal according to at least the first input control signal, wherein the first input control signal has a first signal segment followed by a second signal segment, and a voltage level of the first signal segment is unknown; and a driver circuit, operated according to a supply power, for receiving the output control signal from the control circuit; wherein a voltage of the supply power is settle before the second signal segment of the first input control signal is received by the control circuit; when the supply power is turned on, the driver circuit operates under a specific power state; and when the second signal segment of the first input control signal is received by the control circuit, the driver circuit keeps operating under the specific power state. | 05-14-2015 |