Patent application number | Description | Published |
20110006985 | DISPLAY SURFACE AND CONTROL DEVICE COMBINED THEREWITH - The invention relates to a display surface and a control device combined therewith for a data processing system, wherein a display surface is equipped with photosensitive elements. A photosensitive element is configured as a planar position detector on the basis of a layer made of an organic photoactive material, which on both sides is connected by a planar electrode, wherein at least one electrode inside the circuit thereof has relatively high resistance, wherein the current through an electrode having poor conductivity is measured at several connecting points disposed at a distance from each other and from this conclusions may be drawn about the position of a local conductive connection through the photosensitive layer caused by light absorption. A luminous indicator produces a light spot on the display surface, the spot is detectable by the position detectors and reported to a data processing unit. | 01-13-2011 |
20110115750 | CONTROL SURFACE FOR A DATA PROCESSING SYSTEM - The invention relates to an optical-signal based control surface for a data processing system, said surface being designed as a planar optical fiber, on which photoelectric sensors are provided, the measured signals of which are used to deduce the position of a light signal striking the control surface and said position being associated with a processing mark in the data processing system. A layer having photoluminescent properties is in contact with at least one layer of the planar optical fiber. The light of the light beam shining on the control surface is converted into longer-wave light by way of photoluminescence, said light being coupled into the waveguide, diffusing therein, and being measured by the photoelectric sensors. | 05-19-2011 |
20110266423 | DETECTOR SURFACE - A detector surface which is based on optical signals and arranged as a flexible enveloping surface around the body in order to detect whether and where the illuminated indicator strikes the body. The detector surface composed of one or more planar optical fibers, wherein at least one layer of a planar optical fiber has photoluminescent properties, and wherein photodetectors are arranged on the planar optical fiber such that they can decouple light from the optical fiber and detect it. The planar optical fiber is designed as a film made of a transparent polymer having a thickness of 30 to 500 μm and the photodetector is arranged at a distance from all edges of the optical fiber on the optical fiber. | 11-03-2011 |
20130187033 | LIGHT CURTAIN - A light curtain for the optical detection of shading objects in an area to be monitored, wherein the area to be monitored is repeatedly swept over by a collimated light beam of variable direction. The power of the light crossing the area is measured, shadow boundaries, position and size of a shading object are deduced by an evaluating control from the temporal profile of the measured power with knowledge of the temporal profile of the direction of the light beam. An optical detector area embodied as a planar optical waveguide is arranged along the edge of the area to be monitored, photoluminescent particles being integrated into said optical detector area and one or more photoelectric sensors being fitted to the optical detector area. Using the light curtain, shading objects can be detected with very good resolution, the light curtain can be robust and can have a low production cost. | 07-25-2013 |
20140015806 | INPUT PANEL CONSISTING OF A DISPLAY PANEL AND A PHOTO-SENSITIVE DETECTOR PANEL, FOR A DATA PROCESSING INSTALLATION - An input panel having a display panel and a photosensitive detector panel, for controlling a data processing installation. Also disclosed is a method for operating such an input panel. In one preferred embodiment, the detector panel and the display panel are arranged at a distance from one another and the layer which adjoins the detector panel on the display panel side is an air layer. In a preferred mode of operation, a beam of light which is emitted by a light pointer device onto the input panel for the purpose of controlling the data processing installation has radiation components in two different spectral ranges, one radiation component being in the spectral range of visible light and the second radiation component being in the spectral range of IR light or UV light, with only the radiation component which is present as IR or UV light being absorbed by the detector panel. | 01-16-2014 |
20140022170 | LIGHT CURTAIN AND AN INPUT APPARATUS BASED THEREON FOR A DATA PROCESSING SYSTEM - A light curtain having a light source which emits a light beam which propagates in an area to be monitored by the light curtain and then strikes an optical detector surface. The area to be monitored is arranged in the vicinity of a translucent disc and is oriented parallel to the latter. The light source and detector surface are arranged on that side of the disc which faces away from the area to be monitored. The path of the light beam from the light source to the detector surface runs twice through the plane of the disc and via two mirrors arranged on the edge of the area to be monitored. | 01-23-2014 |
20150049022 | COMPUTER SYSTEM AND A CONTROL METHOD THEREFOR - A computer system that includes a data-processing unit, a touch-sensitive, position-resolving input surface in data communication with the data-processing unit, and a freely movable input device, by which the input surface is to be touched for the purpose of inputting into the data-processing unit. The freely movable input device is a computer mouse, which is in data communication with the data-processing unit. With comparatively low sensor complexity, inter alia, both the absolute position of the computer mouse and also subtle position changes of the computer mouse can therefore be very easily detected by the data-processing unit. | 02-19-2015 |
Patent application number | Description | Published |
20090213674 | Method and device for controlling a memory access and correspondingly configured semiconductor memory - Method and device for controlling a memory access and correspondingly configured semiconductor memory | 08-27-2009 |
20100034056 | Apparatus And System With A Time DelayApparatus And System With A Time Delay Path And Method For Propagating A Timing Event Path And Method For Propagating A Timing Event - Implementations are presented herein that include a time delay path. | 02-11-2010 |
20120020145 | Identification Circuit and Method for Generating an Identification Bit - A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another. | 01-26-2012 |
20120057411 | Latch Based Memory Device - A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach. | 03-08-2012 |
20120307579 | MEMORY RELIABILITY VERIFICATION TECHNIQUES - Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells. | 12-06-2012 |
20130141987 | Latch Based Memory Device - A method of testing a latch based memory device is disclosed. The latch based memory device includes a number of latches, electrical connections and a circuit environment of the latches. A storage functionality of the latches can be tested during a first test phase while a functionality of the electrical connections and the circuit environment of the latches can be tested during a second test phase. | 06-06-2013 |