Patent application number | Description | Published |
20100278485 | METHOD FOR MANUFACTURING OPTICAL COUPLING ELEMENT, OPTICAL TRANSMISSION SUBSTRATE, OPTICAL COUPLING COMPONENT, COUPLING METHOD, AND OPTICAL INTERCONNECT SYSTEM - An optical coupling structure that interfaces between optical devices mounted on a substrate and optical waveguides formed in the substrate. A manufacturing method includes preparing a wafer formed on an inorganic solid material on a dicing tape and cutting the back surface of the wafer to form substantially angled portions using a dicing blade having a point angle. The dicing tape is stripped from the wafer and the wafer is separated at the valleys between the substantially angled portions to obtain an optical coupling element. The obtained optical coupling element is a three-dimensional polyhedral light-reflecting member having a mirror surface corresponding to a surface of the wafer. The obtained optical coupling element is inserted into a trench that opens, substantially perpendicular to an optical waveguide of an optical transmission substrate, in the main surface of the optical transmission substrate to provide a structure for optical coupling with the outside. | 11-04-2010 |
20110153283 | METHOD FOR DESIGNING LAYOUT OF OPTICAL WAVEGUIDES - A method and apparatus to optimally design the layout of a plurality of optical waveguides in a case where one or more crossings occur due to a planar configuration of optical waveguides. Embodiments include a plurality of default routes are set for all of a plurality of waveguides so that each of a plurality of waveguides bundled at an input end is split into two or more waveguides, one split waveguide, together with another split waveguide, forms one or more crossings, and a plurality of split waveguides are bundled at least two separate places at an output end. The number of crossings existing on each of the routes is counted. The default value (splitting ratio) of the cross section (thickness and shape) of each of one waveguide and a plurality of waveguides split from the one waveguide is set on the basis of the counted number of crossings. | 06-23-2011 |
20120267338 | METHOD FOR MANUFACTURING OPTICAL COUPLING ELEMENT, OPTICAL TRANSMISSION SUBSTRATE, OPTICAL COUPLING COMPONENT, COUPLING METHOD, AND OPTICAL INTERCONNECT SYSTEM - An optical coupling structure that interfaces between optical devices mounted on a substrate and optical waveguides formed in the substrate. A manufacturing method includes preparing a wafer formed on an inorganic solid material on a dicing tape and cutting the back surface of the wafer to form substantially angled portions using a dicing blade having a point angle. The dicing tape is stripped from the wafer and the wafer is separated at the valleys between the substantially angled portions to obtain an optical coupling element. The obtained optical coupling element is a three-dimensional polyhedral light-reflecting member having a mirror surface corresponding to a surface of the wafer. The obtained optical coupling element is inserted into a trench that opens, substantially perpendicular to an optical waveguide of an optical transmission substrate, in the main surface of the optical transmission substrate to provide a structure for optical coupling with the outside. | 10-25-2012 |
20140112629 | ALIGNMENT OF SINGLE-MODE POLYMER WAVEGUIDE (PWG) ARRAY AND SILICON WAVEGUIDE (SIWG) ARRAY OF PROVIDING ADIABATIC COUPLING - A method for fabricating, and a structure embodying, a single-mode polymer wave guide array aligned with a polymer waveguide array through adiabatic coupling. The present invention provides a structure having a combination of (i) a stub fabricated on a polymer and (ii) a groove fabricated on a silicon (Si) chip, with which an adiabatic coupling can be realized by aligning (a) a (single-mode) polymer waveguide (PWG) array fabricated on the polymer with (b) a silicon waveguide (SiWG) array fabricated on the silicon chip; wherein, the stub fabricated on the polymer is patterned according to a nano-imprint process, along with the PWG array, in a direction in which the PWG array is fabricated, and the groove fabricated on the silicon chip is fabricated along a direction in which the SiWG array is fabricated. | 04-24-2014 |
20140147083 | CONNECTOR FOR MULTILAYERED OPTICAL WAVEGUIDE - Methods for fabricating connectors for multilayered optical waveguides, as well as apparatuses for multilayered optical waveguides that embody ferrules and connectors. The method of fabricating a connector includes the steps of: stacking in a containing unit of a ferrule, a plurality of optical waveguides that are each preliminarily formed in the shape of layers; and injecting resin or adhesive through a space lying between the plurality of optical waveguides and the containing unit of the ferrule, with the plurality of optical waveguides contained in a stacked manner so that resin or adhesive reaches each of the plurality of optical waveguides. | 05-29-2014 |
Patent application number | Description | Published |
20090213201 | IMAGE FORMING METHOD AND IMAGE FORMING APPARATUS - An image forming method including: forming a liquid receiving particle layer on an intermediate transfer member using a liquid receiving particle that is capable of receiving a recording liquid including a recording material; forming an image of the recording material on a surface of the liquid receiving particle layer by applying a liquid droplet of the recording liquid to the liquid receiving particle layer on the basis of image data and holding the recording material on the surface of the liquid receiving particle layer on the intermediate transfer member; applying a transfer auxiliary liquid in at least a portion of a formation range of the image; and transferring the liquid receiving particle layer to which the recording liquid is applied to a transfer receiving member from the intermediate transfer member, such that the image is interposed between the transfer receiving member and the liquid receiving particle layer is provided. | 08-27-2009 |
20100091064 | IMAGE FORMING APPARATUS AND IMAGE FORMING METHOD - An image forming apparatus includes: a supply unit that supplies liquid absorbing particles to receive a liquid; a transporting unit that transports the liquid absorbing particles supplied by the supply unit; and a ejecting unit that ejects liquid droplets to the liquid absorbing particles transported by the transporting unit, the ejecting unit having: an ink ejecting part that ejects ink; and a dampening solution ejecting part that ejects a dampening solution to dampen the liquid absorbing particles, the ink ejecting part being provided on an upstream side of the dampening solution ejecting part in an image forming direction. | 04-15-2010 |
20100123748 | LIQUID DROPLET EJECTING APPARATUS, LIQUID DROPLET EJECTING METHOD AND COMPUTER READABLE MEDIUM STORING A PROGRAM - A liquid droplet ejecting apparatus includes a liquid ejecting module and a measurement section. The liquid ejecting module includes a pressure chamber that has a piezoelectric element and an ejecting nozzle, and a supply passage that supplies liquid into the pressure chamber, and the liquid ejecting module configured to eject, from the ejecting nozzles, liquid which is supplied to the pressure chamber through the supply passage. The measurement section measures an admittance or a phase difference between a voltage applied to the piezoelectric element and a current through the liquid ejecting module when the voltage is applied. | 05-20-2010 |
20150158311 | DROPLETS DRYING DEVICE, COMPUTER READABLE MEDIUM STORING PROGRAM FOR DROPLETS DRYING, AND IMAGE FORMING APPARATUS - A droplets drying device includes: an illuminating unit that applies infrared laser light to droplets that have been ejected onto a recording medium by an ejecting unit that ejects droplets in accordance with an image to be formed; and a control unit that controls at least one of timing, a position or positions, and an amount or amounts of application of infrared laser light to the droplets by the illuminating unit in accordance with an attribute that influences image quality of an image formed. | 06-11-2015 |
Patent application number | Description | Published |
20160094003 | LASER DEVICE, IGNITION SYSTEM, AND INTERNAL COMBUSTION ENGINE - A laser device is provided including a light source configured to emit light, a laser resonator which the light emitted from the light source enters, a first optical element configured to increase a divergence angle of the light emitted from the laser resonator, a second optical element configured to collimate the light whose divergence angle is increased by the first optical element, and a third optical element configured to collect and condense the light collimated by the second optical element. | 03-31-2016 |
20160094006 | LASER DEVICE, IGNITION SYSTEM, AND INTERNAL COMBUSTION ENGINE - A laser device is provided including a light source configured to emit light, a light transmission member configured to transmit the light emitted from the light source, a plurality of optical elements disposed in an optical path of the light transmitted by the light transmission member, a laser resonator which the light passed through the plurality of optical elements enter, and an adjuster configured to adjust a position of at least one of the plurality of optical elements. | 03-31-2016 |
20160094009 | LASER DEVICE, IGNITION SYSTEM, AND INTERNAL COMBUSTION ENGINE - A laser device is provided including a surface emitting laser array configured to emit light, an optical system disposed in an optical path of light that is emitted from the surface emitting laser, a laser resonator which the light passed through the optical system enters, where the optical system includes a first optical element configured to collimate the light emitted from the surface emitting laser, and a second optical element configured to collect and condense the light collimated by the first optical element. | 03-31-2016 |
Patent application number | Description | Published |
20090073277 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD AND IMAGE PICKUP APPARATUS - An image processing apparatus is provided wherein a plurality of reference blocks of a size equal to that of a target block which has a predetermined size and includes a plurality of pixels set to a predetermined position in a target screen are set in a search range set on a reference screen and a motion vector is detected based on a positional displacement amount, on the screen, of that one of the reference blocks which has the highest correlation to the target block from the target block, comprising, a compression section, a first storage section, a decompression decoding section, a second storage section, and a mathematical operation section. | 03-19-2009 |
20090103621 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - Described herein is an image processing apparatus for calculating a motion vector between two screen images including a target screen image and a reference screen image, including: a base face motion vector calculation section; a high-accuracy base face motion vector calculation section; a reduction face motion vector calculation section; a high-accuracy reduction face motion vector calculation section; first and second base face search range determination sections; and a selection section configured to select a calculation section to be used from among the base face motion vector calculation section, high-accuracy base face motion vector calculation section, reduction face motion vector calculation section and high-accuracy reduction face motion vector calculation section and select whether the first or second base face search range determination section should be used and then select, where use of any of the determination sections is determined, a determination section to be used from between the determination sections. | 04-23-2009 |
Patent application number | Description | Published |
20110244328 | NEGATIVE ELECTRODE FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY, NONAQUEOUS ELECTROLYTE SECONDARY BATTERY USING THE SAME, AND METHOD FOR MANUFACTURING NEGATIVE ELECTRODE FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY - There is provided a negative electrode for a nonaqueous electrolyte secondary battery in which when a battery is formed, the energy density is high, and moreover, the decrease in charge and discharge capacity is small even if charge and discharge are repeated. By using silicon oxide particles having a particle diameter in a particular range as a starting raw material, and heating these particles in the range of 850° C. to 1050° C., Si microcrystals are deposited on the surfaces of the particles. Then, by performing doping of Li, a structure comprising a plurality of protrusions having height and cross-sectional area in a particular range is formed on the surfaces. The average value of the height of the above protrusions is 2% to 19% of the average particle diameter of the above lithium-containing silicon oxide particles. By using the lithium-containing silicon oxide particles obtained by the above means as a negative electrode active material, a negative electrode for a nonaqueous electrolyte secondary battery is fabricated. | 10-06-2011 |
20110274966 | NONAQUEOUS ELECTROLYTIC SOLUTION SECONDARY BATTERY AND METHOD FOR PRODUCING THE SAME - An exemplary embodiment of the invention provides a nonaqueous electrolytic solution secondary battery in which capacity deterioration associated with a charge/discharge cycle at a high temperature (45° C. or higher) can be prevented. An exemplary embodiment of the invention is a nonaqueous electrolytic solution secondary battery, comprising an electrode element in which a cathode and an anode are stacked, a nonaqueous electrolytic solution which contains at least one of carbonate solvent, and a gel in an outer packaging body; wherein the anode comprises a silicon oxide represented by SiO | 11-10-2011 |
20130244086 | NEGATIVE ELECTRODE FOR SECONDARY BATTERY AND METHOD FOR MANUFACTURING THE SAME, AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERY - Provided are a negative electrode for a secondary battery realizing satisfactory cycle characteristics and a method for manufacturing the same, and a nonaqueous electrolyte secondary battery having satisfactory cycle characteristics. A negative electrode for a secondary battery formed by bonding a negative electrode active material to a negative electrode collector with a negative electrode binder, in which the negative electrode binder is a polyimide or a polyamide-imide, and the negative electrode collector is a Cu alloy containing at least one metal (a) selected from the group consisting of Sn, In, Mg and Ag and has a conductivity of 50 IACS % or more. The negative electrode for a secondary battery can be manufactured by a method including forming a negative electrode layer containing the negative electrode active material and the precursor of the negative electrode binder on the negative electrode collector; and bonding the negative electrode active material to the negative electrode collector with the negative electrode binder by curing the precursor of the negative electrode binder at 250 to 350° C. | 09-19-2013 |
20130280594 | NONAQUEOUS ELECTROLYTE SECONDARY BATTERY - In a nonaqueous electrolyte secondary battery using silicon and silicon oxide as a negative electrode active material, the charge and discharge cycle characteristics are improved. A nonaqueous electrolyte secondary battery in the exemplary embodiment comprises a sheet-shaped negative electrode comprising a negative electrode active material layer comprising a composite of silicon and silicon oxide formed on a negative electrode current collector, and a sheet-shaped positive electrode comprising a positive electrode active material layer formed on a positive electrode current collector, wherein the negative electrode is disposed opposed to the positive electrode via a separator, a peripheral edge portion of the negative electrode active material layer is disposed within a peripheral edge portion of the positive electrode active material layer, and a relationship of 1.0010-24-2013 | |
Patent application number | Description | Published |
20110303972 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer. | 12-15-2011 |
20120146053 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls. | 06-14-2012 |
20120282743 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode. | 11-08-2012 |
20130240828 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion. | 09-19-2013 |
20150097189 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer. | 04-09-2015 |