Patent application number | Description | Published |
20100084735 | SEMICONDUCTOR ASSEMBLY AND METHOD FOR FORMING SEAL RING - A method for forming a seal ring is disclosed. First, a substrate including a MEMS region, a logic region and a seal ring region is provided. Second, a trench is formed in the MEMS region and multiple recesses are formed in the seal ring region. An oxide fills the trench and the recesses. Later, a MOS is form in the logic region and a dielectric layer is formed on the substrate. Then, an etching procedure is carried out to partially remove the dielectric layer and simultaneously remove the oxide in the multiple recesses completely to form a seal ring space. Afterwards, a metal fills the seal ring space to from the seal ring. | 04-08-2010 |
20100096726 | METAL CAPACITOR AND METHOD OF MAKING THE SAME - A method of making a metal capacitor includes the following steps. A dielectric layer having a metal interconnection and a capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the metal interconnection and the dielectric layer can be prevented. | 04-22-2010 |
20110012227 | SEMICONDUCTOR ASSEMBLY - A semiconductor assembly includes a substrate with at least a CMOS region and a seal ring region and an optional micro electro mechanical system (MEMS) region, a shallow trench isolation disposed in the CMOS region of the substrate, an optional micro electro mechanical system device disposed in the micro electro mechanical system region, a plurality of recesses disposed in the seal ring region of the substrate, a first metal-oxide semiconductor disposed in the CMOS region, a dielectric layer disposed on the substrate and on the recesses, and a seal ring disposed in the seal ring region and embedded in the dielectric layer to cover and fill up the recesses, wherein the seal ring region surrounds at least the CMOS region and the optional MEMS region. | 01-20-2011 |
20120098094 | METAL CAPACITOR AND METHOD OF MAKING THE SAME - A metal capacitor structure is disclosed. The metal capacitor structure includes: a dielectric layer having a first region and a second region, a dielectric constant of the dielectric layer in the second region being higher than a dielectric constant of the dielectric layer in the first region; a dual damascene metal interconnection positioned in the first region; and a damascene capacitor electrode positioned in the second region. | 04-26-2012 |
20120115301 | METAL CAPACITOR AND METHOD OF MAKING THE SAME - A method of making a metal capacitor includes the following steps. A dielectric layer having a dual damascene metal interconnection and a damascene capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the damascene capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the dual damascene metal interconnection and the dielectric layer can be prevented. | 05-10-2012 |
20130015504 | TSV STRUCTURE AND METHOD FOR FORMING THE SAMEAANM Kuo; Chien-LiAACI Hsinchu CityAACO TWAAGP Kuo; Chien-Li Hsinchu City TWAANM Yang; Chin-ShengAACI Hsinchu CityAACO TWAAGP Yang; Chin-Sheng Hsinchu City TWAANM Lin; Ming-TseAACI Hsinchu CityAACO TWAAGP Lin; Ming-Tse Hsinchu City TW - A TSV structure includes a wafer including a first side and a second side, a through via connecting the first side and the second side, a through via dielectric layer covering the inner wall of the through via, a conductive layer which fills up the through via and consists of a single material to be a seamless TSV structure, a first dielectric layer covering the first side and surrounding the conductive layer as well as a second dielectric layer covering the second side and part of the through via dielectric layer but partially covered by the conductive layer. | 01-17-2013 |
20130015556 | SUSPENDED BEAM FOR USE IN MEMS DEVICEAANM YANG; Chin-ShengAACI Hsinchu CityAACO TWAAGP YANG; Chin-Sheng Hsinchu City TW - A suspended beam includes a substrate, a main body and a first metal line structure. A first end of the main body is fixed onto the substrate. A second end of the main body is suspended. The first metal line structure is embedded in the main body. The width of the first metal line structure is smaller than the width of the main body. | 01-17-2013 |
20130026641 | CONDUCTOR CONTACT STRUCTURE AND FORMING METHOD, AND PHOTOMASK PATTERN GENERATING METHOD FOR DEFINING SUCH CONDUCTOR CONTACT STRUCTURE - A conductor contact structure includes a conductor line, a dielectric layer and a contact hole. The conductor line includes a first zone and a second zone. The first zone extends along a symmetry axis and is symmetrical with respect to the symmetry axis. The second zone extends along the symmetry axis but is not symmetrical with respect to the symmetry axis. A distance between a first edge of the second zone and the symmetry axis is greater than a distance between a second edge of the second zone and the symmetry axis. A contact hole is formed in the dielectric layer and in communication with the second zone. A diameter of the contact hole is smaller than a distance between the first edge and the second edge of the second zone. | 01-31-2013 |
20130056858 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A method for fabricating integrated circuit is provided. First, a substrate having a micro electromechanical system (MEMS) region is provided. A first interconnect structure and a hard mask layer have been disposed on the MEMS region in sequence. Next, an anisotropic etching process is performed by using the hard mask layer as a photo mask to etch a portion of the first interconnect structure exposed by the hard mask layer. Accordingly, a MEMS structure is formed. A portion of the substrate in MEMS region is exposed by the MEMS structure. Then, an isotropic etching process is performed for removing the portion of the substrate in MEMS region to form a cavity with a center region and a ring-like indentation region. The center region is surrounded by the ring-like indentation region and the MEMS structure suspends above the cavity. An integrated circuit is also provided. | 03-07-2013 |
20130168742 | INTEGRATED CIRCUIT CONFIGURATION AND FABRICATING METHOD THEREOF - An integrated circuit configuration includes a substrate, a diffusion region, a gate structure, an extension conductor structure, a dielectric layer, a contact structure, and a metal conductor line. The diffusion region is formed in the substrate. The gate structure is formed over the substrate and spanned across the diffusion region. The extension conductor structure is formed over the semiconductor substrate and contacted with the diffusion region. The extension conductor structure is extended externally to a first position along a surface of the substrate, wherein the first position is outside the diffusion region. The dielectric layer is formed over the substrate, the gate structure and the extension conductor structure. The contact structure is penetrated through the dielectric layer to be contacted with the first position of the extension conductor structure. The metal conductor line is formed on the dielectric layer and contacted with the contact structure. | 07-04-2013 |
20140361359 | SONOS DEVICE AND METHOD FOR FABRICATING THE SAME - A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer. | 12-11-2014 |
20150236150 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided. | 08-20-2015 |
Patent application number | Description | Published |
20080237144 | METHOD FOR REMOVING MICRO-BUBBLES AND/OR PARTICLES FROM LIQUID, LIQUID SUPPLY APPARATUS AND IMMERSION EXPOSURE APPARATUS - A liquid supply apparatus capable of removing micro-bubbles and particles is described, including a pipe, a laser provider and at least one micro-bubble/particle outlet. The laser provider provides a laser crossing the pipe, wherein the laser is provided in a manner such that a micro-bubble/particle blocking/repelling barrier is formed crossing the pipe blocking or repelling micro-bubbles, particles or both in the liquid in the pipe. The micro-bubble/particle outlet is disposed on the pipe between the barrier and the liquid inlet of the pipe, adjacent to the barrier for discharging micro-bubbles, particles or both. | 10-02-2008 |
20080237659 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. Devices are formed on a core region and a non-core region in a substrate. A strain process is performed to the device on the core region but is not performed to the device on the non-core region. | 10-02-2008 |
20080246061 | STRESS LAYER STRUCTURE - A stress layer structure disposed on a substrate including a device region and a non-device region is provided. The device region includes active regions and a non-active region. The stress layer structure has stress patterns, at least one partition line, and at least one dummy stress pattern. Each of the stress patterns is disposed on the substrate of each of the active regions, respectively. The partition line exposes a portion of the substrate and divides the two adjacent stress patterns. The dummy stress pattern is disposed on the substrate in the partition line. | 10-09-2008 |
20080296695 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor is provided. The semiconductor device includes a transistor, a first strain layer and a second strain layer on a substrate. The first strain layer is configured at the periphery of the transistor. The second strain layer covers the transistor and a region exposed by the first strain layer. The stress provided by the second strain layer is different from that by the first strain layer. | 12-04-2008 |
20090079083 | INTERCONNECT STRUCTURE AND FABRICATING METHOD OF THE SAME - A fabricating method of an interconnect structure is provided. A first dielectric layer is formed on a substrate for covering an air gap region and a non-air gap region. Next, interconnects are formed in the first dielectric layer on the air gap region and in the first dielectric layer on the non-air gap region. Then, a cap layer is formed on the first dielectric layer. Thereafter, on the air gap region, a portion of the cap layer and a portion of the first dielectric layer are removed for forming first openings, and thereby a portion of the first dielectric layer are left between the interconnects for forming support pillars. After that, a second dielectric layer is formed over the substrate for covering the cap layer and the first openings, so as to form an air gap in each of the first openings. | 03-26-2009 |
20090212368 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel regions of these transistors are the same, but at least one source or drain region has a width along a channel length direction and the width is different from widths of other source or drain regions. The strain layers include first and second strain layers embedded separately at two sides of each gate structure in the substrate. A first width of each first strain layer along the channel length direction is the same, and a second width of each second strain layer along the channel length direction is the same. | 08-27-2009 |
20100090749 | MULTI-FUNCTION CHIP - A multi-function chip including a circuit and at least one control circuit is provided. The circuit having multiple functions includes an interconnection. The interconnection has at least one resistance-variable segment. The control circuit is electronically connected to the resistance-variable segment. One of the functions is carried out by adjusting the resistance of the resistance-variable segment with the control circuit. | 04-15-2010 |
20110186750 | METHOD FOR REMOVING MICRO-BUBBLES AND/OR PARTICLES FROM LIQUID, LIQUID SUPPLY APPARATUS AND IMMERSION EXPOSURE APPARATUS - A liquid supply apparatus capable of removing micro-bubbles and particles is described, including a pipe, a laser provider and at least one micro-bubble/particle outlet. The laser provider provides a laser crossing the pipe, wherein the laser is provided in a manner such that a micro-bubble/particle blocking/repelling barrier is formed crossing the pipe blocking or repelling micro-bubbles, particles or both in the liquid in the pipe. The micro-bubble/particle outlet is disposed on the pipe between the barrier and the liquid inlet of the pipe, adjacent to the barrier for discharging micro-bubbles, particles or both. | 08-04-2011 |
20110186751 | METHOD FOR REMOVING MICRO-BUBBLES AND/OR PARTICLES FROM LIQUID, LIQUID SUPPLY APPARATUS AND IMMERSION EXPOSURE APPARATUS - A liquid supply apparatus capable of removing micro-bubbles and particles is described, including a pipe, a laser provider and at least one micro-bubble/particle outlet. The laser provider provides a laser crossing the pipe, wherein the laser is provided in a manner such that a micro-bubble/particle blocking/repelling barrier is formed crossing the pipe blocking or repelling micro-bubbles, particles or both in the liquid in the pipe. The micro-bubble/particle outlet is disposed on the pipe between the barrier and the liquid inlet of the pipe, adjacent to the barrier for discharging micro-bubbles, particles or both. | 08-04-2011 |
20110241212 | STRESS LAYER STRUCTURE - A stress layer structure includes an active stress portion and a dummy stress portion, both formed of a stress material and disposed on the substrate. The active stress portion includes first and second active stress patterns in a region where active devices are formed. The first and second active stress patterns coverrespective active regions, and are separated from each other. The dummy stress portion includes a first dummy stress pattern formed directly on the substrate and disposed between and separated from the first and second active stress patterns. | 10-06-2011 |