Hung, Hsinchu
Che-Lun Hung, Hsinchu TW
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20120074401 | TEST PATTERN FOR DETECTING PIPING IN A MEMORY ARRAY - A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided. | 03-29-2012 |
20160041201 | DIE STRUCTURE, CONTACT TEST STRUCTURE, AND CONTACT TESTING METHOD UTILIZING THE CONTACT TEST STRUCTURE - A die structure is described, including a device area and a contact test area. The device area has therein a device structure including a first contact plug. The contact test area has therein a contact test structure that includes a second contact plug and is different from the device structure. The contact test structure is also described, including a well, a heavily doped region in the well, and a contact plug, wherein the heavily doped region and the well are both of N-type or are both of P-type, and the contact plug is disposed over the heavily doped region. | 02-11-2016 |
Chen Chun Hung, Hsinchu TW
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20140063472 | Laser Scanning Projection Apparatus with Phase Detection and Compensation - A laser scanning projection apparatus includes an illumination unit, a projection surface, a scanning mirror, a projection window, an optical sensor, and a controlling unit. The projection window includes a transmissible part and a blocking part. A reflection-differential pattern is formed on the blocking part. When the laser beam reflected by the scanning mirror is projected on the transmissible part, the laser beam is transmitted through the transmissible part and projected on the projection surface. When the laser beam reflected by the scanning mirror is projected on the reflection-differential pattern, a reflective beam with different intensities is reflected by the reflection-differential pattern. The controlling unit calculates a phase difference between an actual projection position and a predetermined projection position of the laser beam according to the sensing signal, and compensating a subsequent image frame according to the phase difference. | 03-06-2014 |
Cheng-Chou Hung, Hsinchu TW
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20110068415 | Radio Frequency Device and Method for Fabricating the Same - A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type. | 03-24-2011 |
Cheng-Hsien Hung, Hsinchu TW
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20080205178 | DRAM writing ahead of sensing scheme - This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated. | 08-28-2008 |
Chen-Ming Hung, Hsinchu TW
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20110037399 | DIMMER CIRCUIT OF LIGHT EMITTING DIODE AND ISOLATED VOLTAGE GENERATOR AND DIMMER METHOD THEREOF - An isolated configuration dimmer circuit of a light emitting diode (LED) applied to a conventional triac dimmer and a dimmer method are provided. When a dimmer phase angle of the triac dimmer is regulated, a second side winding of a transformer of the isolated configuration produces a pulse width corresponding to a modulated alternating current (AC) voltage, so as to regulate the pulse width of a driving signal output by the second side winding of the transformer. In addition, the dimmer circuit regulates the magnitude of a current flowing through the light emitting diode (LED) according to the pulse width corresponding to the modulated AC voltage. Accordingly, the dimmer circuit regulates the pulse width and the magnitude of the current flowing through the LED according to the dimmer phase angle of the triac dimmer. Therefore, a dimmer range of the LED can be increased. | 02-17-2011 |
Che-Pin Hung, Hsinchu TW
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20090185395 | BACK-LIGHT MODULE - A back-light module includes a light-guiding plate and a light source. The light-guiding plate has a lateral inlet surface. The light source is arranged at one side of the lateral inlet surface. The light source has a plurality of light-emitting diodes which are disposed in a line and at interval. A gap is formed between the adjacent light-emitting diodes. The lateral inlet surface dispose a plurality of convex lenses, each of the convex lenses has a convex surface facing to the corresponding gap between the adjacent light-emitting diodes. | 07-23-2009 |
Chia-Chien Hung, Hsinchu TW
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20090277480 | METHOD OF REDUCING SURFACE RESIDUAL DEFECT - A method of reducing residual defect on a dielectric surface includes performing a treatment process of the dielectric surface prior to a lithograph process. The treatment process includes at least a first wet chemical treatment step and a second wet chemical treatment step. | 11-12-2009 |
Chia-Ho Hung, Hsinchu TW
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20150022285 | BANDPASS FILTER - A bandpass filter includes a first uniform impedance resonator comprising a first microstrip line and a second microstrip line, a second uniform impedance resonator which is axisymmetric to the first uniform impedance resonators, a first asymmetric stepped-impedance resonator comprising a third microstrip line and a fourth microstrip line, a second asymmetric stepped-impedance resonator which is axisymmetric to the first asymmetric stepped-impedance resonator, a third asymmetric stepped-impedance resonator consisting of a fifth microstrip line and a sixth microstrip line, a fourth asymmetric stepped-impedance resonator which is axisymmetric to the third asymmetric stepped-impedance resonator, a input consisting of a seventh microstrip line and connecting with the first microstrip line, and a output which is axisymmetric to the input and connects with the second uniform impedance resonator. | 01-22-2015 |
Chia-Hung Hung, Hsinchu TW
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20080280384 | SOLID-STATE LIGHT EMITTING DISPLAY AND FABRICATION METHOD THEREOF - A solid-state light emitting display and a fabrication method thereof are proposed. The light emitting display includes a metallic board formed with conductive circuits, and a plurality of luminous microcrystals disposed on a surface of the metallic board and electrically connected to the conductive circuits. The metallic board provides the features of lightness and thinness, and flexibility, and the luminous microcrystals are in the form of light emitting components, so as to improve the luminous efficiency of display and attain the effect of environmental protection and energy saving, thereby providing display technology with performance satisfactory for various display requirements. | 11-13-2008 |
Chia-Lung Hung, Hsinchu TW
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20080290375 | INTEGRATED CIRCUIT FOR VARIOUS PACKAGING MODES - The present invention provides an integrated circuit suitable for various packaging modes. This integrated circuit includes: a core circuit, a plurality of pads, and a selection circuit. The selection circuit is coupled between the core circuit and the pads for determining the connection state between the core circuit and the pads based on a control signal. When the control signal provides a first value, the core circuit and the pads will be in a first connection state, and the integrated circuit will be applied with a single-die package. However, when the control signal provides a second value, the core circuit and the pads will be in the second connection state, and the integrated circuit will be applied with a multi-die package. | 11-27-2008 |
20100188574 | DEVICE AND METHOD FOR CONTROLLING FRAME INPUT AND OUTPUT - A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock. | 07-29-2010 |
Chia-Yu Hung, Hsinchu TW
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20080272480 | Land grid array semiconductor package - An LGA (Land Grid Array) semiconductor package mainly comprises a substrate, a chip, a soldering layer and a foot stand. The chip is disposed on a top surface of the substrate and is electrically connected to a plurality of metal pads formed on a bottom surface of the substrate. The soldering layer is disposed on the metal pads with a first thickness slightly protruded from the bottom surface of the substrate. Additionally, the foot stand is disposed under the substrate with a second thickness protruded from the bottom surface of the substrate, wherein the second thickness is greater than the first thickness. Therefore, the soldering layer of the LGA semiconductor package is free from scratches and damages during shipping and handling processes. Moreover, the LGA semiconductor package can be surface-mounted to a printed circuit board with pre-applied solder or pre-mounted solder balls to increase the implementations of LGA semiconductor packages. | 11-06-2008 |
Chi-Chang Hung, Hsinchu TW
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20080304484 | METHOD FOR OPERATING MULTIPOINT CONTROL SYSTEM - The present invention provides method for operating a multipoint control system. It utilizes start packets pass through every one of controlled units which could be modified and transmitted to the next stage to achieve addressing for all of the system. The method comprises providing the multipoint control system, wherein the multipoint control system includes a plurality of controlled units serially connected, each of the controlled units has a execution unit and an interpretive unit, each of the interpretive unit has a data processing unit and a memory unit; transmitting an information stream by a controller, wherein the information stream includes a first start packet and a plurality of first data packets, the first start packet includes a first leading message, a first address, and a first length message; modifying the first address by each of the data processing units included in each of the interpretive units according to the first leading message and transmitting to the next stage; retrieving the first data packet corresponding to the first address by each of the interpretive units according to the first address, the first length message; and enabling each of the execution units included in each of the interpretive units according to content of each of the first data packets. | 12-11-2008 |
Chien-Chung Hung, Hsinchu TW
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20090003043 | Method for switching magnetic moment in magnetoresistive random access memory with low current - A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third magnetic field in a third direction opposite to the first direction, turning off the second magnetic field, and turning off the third magnetic field. A method for switching magnetic moments in an MRAM memory cell includes providing a magnetic field in a direction forming a blunt angle with a direction of a bias magnetic field. A method for reading an MRAM device includes partially switching magnetic moments in a reference memory cell to generate a reference current; measuring a read current through a memory cell to be read; and comparing the read current with the reference current. | 01-01-2009 |
20090010087 | DATA WRITE IN CONTROL CIRCUIT FOR TOGGLE MAGNETIC RANDOM ACCESS MEMORY - A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a transmission gate connected to the first transistor, a comparator having two input terminal connected to the first transistor, a storage capacitor having one end connected to the first transistor and the other end connected to a power source or a ground, and a logic circuit having one end connected to the output terminal of the comparator and the other end receiving data to be written in. | 01-08-2009 |
20140175457 | SIC-BASED TRENCH-TYPE SCHOTTKY DEVICE - A SiC-based trench-type Schottky device is disclosed. The device includes: a SiC substrate having first and second surfaces; a first contact metal formed on the second surface and configured for forming an ohmic contact on the substrate; a drift layer formed on the first surface and including a cell region and a termination region enclosing the cell region; a plurality of first trenches with a first depth formed in the cell region; a plurality of second trenches with a second depth less than the first depth; a plurality of mesas formed in the substrate, each defined between neighboring ones of the trenches; an insulating layer formed on sidewalls and bottoms of the trenches; and a second contact metal formed on the mesas and the insulating layer, extending from the cell region to the termination region, and configured for forming a Schottky contact on the mesas of the substrate. | 06-26-2014 |
20160005883 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode. | 01-07-2016 |
Chien-Hsiang Hung, Hsinchu TW
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20140110569 | Optical Head For Receiving Light And Optical System Using The Same - An optical head for receiving incident light is provided. The optical head comprises a transmissive cosine corrector and a reflector disposed to face the transmissive cosine corrector. The transmissive cosine corrector is disposed in an optical path of the incident light and shields the reflector from the incident light. The transmissive cosine corrector converts the incident light to scattered light having a Lambertian pattern. The reflector has an optical output section that transmits the scattered light and a reflective section that reflects the scattered light to the transmissive cosine corrector and/or the other portions of the reflective sections. An optical system using the optical head is also provided. | 04-24-2014 |
Chih-Hung Hung, Hsinchu TW
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20100059718 | Fabrication of carbon nanotubes reinforced polymer composite bipolar plates for fuel cell - A composite bipolar plate for a polymer electrolyte membrane fuel cell (PEMFC) is prepared as follows: a) compounding vinyl ester and graphite powder to form bulk molding compound (BMC) material, the graphite powder content ranging from 60 wt % to 95 wt % based on the total weight of the graphite powder and vinyl ester, wherein carbon nanotubes together with a polyether amine dispersant or modified carbon nanotubes 0.05-10 wt %, based on the weight of the vinyl ester resin, are added during the compounding; b) molding the BMC material from step a) to form a bipolar plates having a desired shaped at 80-200° C. and 500-4000 psi. | 03-11-2010 |
Ching-Fa Hung, Hsinchu TW
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20140078002 | ANTENNA - An antenna includes an oscillating member and a grounding member arranged toward each other. The oscillating member includes a main body and a first extending section. The first extending section is projected from a first end of the main body toward the grounding member. The grounding member includes a main body, a second extending section, a third extending section, a fourth extending section and a grounding section. The second extending section is projected from a third end of the main body toward the oscillating member; the third extending section is projected from a fourth end of the main body toward the oscillating member; the grounding section is projected from the main body toward the oscillating member. The second extending section is the only one to electrically connect the oscillating member and the grounding member. The grounding section has a grounding point as a ground of the antenna. | 03-20-2014 |
Ching-Wei Hung, Hsinchu TW
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20090230543 | Semiconductor package structure with heat sink - A semiconductor package structure with a heat sink is disclosed herein. The semiconductor package structure includes a substrate having a chip mounting area and a plurality of through holes surrounding the chip mounting area; a chip set on the chip mounting area and electrically connected to the substrate; a heat sink covering the chip, wherein the heat sink has a plurality of support portions extending from the upper surface to the lower surface of the substrate via those through holes; and a molding compound covering the chip, a portion of the substrate and the heat sink. Those support portions of the heat sink are utilized to improve the heat dissipation efficiency and the warpage issue of the package. | 09-17-2009 |
20090236739 | SEMICONDUCTOR PACKAGE HAVING SUBSTRATE ID CODE AND ITS FABRICATING METHOD - A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code. The complexity of the semiconductor packaging processes is not increased and the circuits of the substrates are not easily damaged. | 09-24-2009 |
20110062577 | SUBSTRATE AND PACKAGE WITH MICRO BGA CONFIGURATION - A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes. | 03-17-2011 |
Chiun-Luen Hung, Hsinchu TW
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20150120988 | Method of Accessing Data in Multi-Layer Cell Memory and Multi-Layer Cell Storage Device Using the Same - A method of accessing data in a multi-layer cell (MLC) memory includes using single-layer cell (SLC) configuration to transfer a portion of a plurality of memory units in the MLC memory to an SLC area to form a plurality of MLC memory units and a plurality of SLC memory units; storing data in the plurality of SLC memory units when the data is assigned to be stored in an MLC memory unit; mapping the MLC memory unit to the SLC memory units; reading the data by obtaining the data in the SLC memory units corresponding to the MLC memory unit; and reallocating the SLC memory units to use MLC configuration when an update of data is involved in the MLC memory unit or a new data is assigned to be stored in at least one of the SLC memory units. | 04-30-2015 |
Chi-Yuan Hung, Hsinchu TW
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20140107294 | EXTENDED FILM AND THE MANUFACTURING METHOD THEREOF - An extended film and a manufacturing method thereof are provided. The extended film includes a poly(lactic acid) and a block copolymer, wherein the block polymer includes a first block, a second block and a third block that connected with each other by chemical bonds. The extended film is formed by steps of mixing poly(lactic acid) and the block copolymer to form a mixture, compressing the mixture to form a board body and extending the board body to form an extended film, thereby forming an extended film having properties of high thermal-resistance and high transparency, the film thus obtained is applicable for packaging use. | 04-17-2014 |
Chung-Chih Hung, Hsinchu TW
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20110175763 | DIGITAL-TO-ANALOG CONVERTER - The present invention relates to a digital-to-analog converter comprising a differentiation circuit, a conversion circuit, and an integration circuit. The differentiation circuit receives and differentiates a digital signal for producing a differentiation signal. The conversion circuit is coupled to the differentiation circuit. It receives the differentiation signal and produces a conversion signal according to a clock signal and the differentiation signal. The integration circuit is coupled to the conversion circuit. It receives and integrates the conversion signal for producing an analog signal. Thereby, the purpose of reducing distortion noises can be achieved. | 07-21-2011 |
Chung-Hsiung Hung, Hsinchu TW
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20110173512 | MEMORY AND METHOD FOR CHECKING READING ERRORS THEREOF - A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index. | 07-14-2011 |
20130086350 | METHOD AND SYSTEM FOR ENHANCED PERFORMANCE IN SERIAL PERIPHERAL INTERFACE - A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed. | 04-04-2013 |
20140237207 | METHOD AND SYSTEM FOR ENHANCED PERFORMANCE IN SERIAL PERIPHERAL INTERFACE - A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed. | 08-21-2014 |
Chung Pei Hung, Hsinchu TW
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20110016047 | FINANCIAL TRANSACTION SYSTEM, AUTOMATED TELLER MACHINE (ATM), AND METHOD FOR OPERATING AN ATM - A financial transaction system is provided. The financial transaction system includes a server and at least one automated teller machine (ATM). In response to a request from a user, the server issues a one-time password (OTP) to the user's mobile device. The ATM receives an OTP from the user and sends the received OTP to the server for verification, in order to perform a financial transaction operation. | 01-20-2011 |
20110149533 | INTEGRATED CIRCUIT FILM FOR SMART CARD - An integrated circuit (IC) film for a smart card is provided. The IC film includes a flexible printed circuit (FPC) board, first electrical contacts, second electrical contacts, and an IC chip. The first electrical contacts are disposed on a first side of the FPC board, and the second electrical contacts are disposed on a second side of the FPC board. The IC chip is disposed on the FPC board and bonded to the leads of the FPC board to thereby form electrical connection. The total thickness of the FPC board and the chip is not larger than 0.5 mm. | 06-23-2011 |
Chun-Hsung Hung, Hsinchu TW
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20120210193 | MEMORY AND METHOD FOR CHECKING READING ERRORS THEREOF - A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index. | 08-16-2012 |
I-Peng Hung, Hsinchu TW
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20090002989 | INTEGRALLY FORMED REFLECTOR STRUCTURE, BACKLIGHT MODULE USING THE SAME REFLECTOR STRUCTURE AND METHOD FOR ASSEMBLING THE SAME BACKLIGHT MODULE - The present invention discloses an integrally formed reflector structure, a backlight module using the same reflector structure and a method for assembling the same module. An accommodation spacer and a plurality of lamp-support members are formed on a reflector baseplate with a vacuum-forming method, and a plurality of extension portions extend from the edges of the accommodation space. Further, pluralities of support pins, reflecting members, lamp-fixing members, positioning members, bent portions, etc. are formed in the appropriate positions of the reflector baseplate or the extension portions with a vacuum-forming method. Besides, the extension portions are bent from the bent portions to form a plurality of grooves, which are used to secure optical films in cooperation with the positioning members. | 01-01-2009 |
Jui-Hui Hung, Hsinchu TW
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20140317467 | METHOD OF DETECTING AND CORRECTING ERRORS WITH BCH ENGINES FOR FLASH STORAGE SYSTEM - A method of detecting and correcting errors with BCH engines for flash storage system is provided and the steps of the method comprise: deciding the number i of sub-channels CH1˜CHi divided from a data channel; deriving a width selection of each sub-channel CHi; checking if the sum of width of each sub-channel CHi is equal to the data channel or not; if yes, run next step; if not, go back to the precious step; and connecting each BCH engine BCHi to each sub-channel CHi with a bus by one-by-one mapping. | 10-23-2014 |
20150012801 | METHOD OF DETECTING AND CORRECTING ERRORS WITH BCH AND LDPC ENGINES FOR FLASH STORAGE SYSTEMS - A method of detecting and correcting errors with BCH and LDPC engines for flash storage systems is provided and the steps of the method comprise: deciding the number i of sub-channels CH1˜CHi divided from the data channel depending on requirement; deriving the width selection of each sub-channel CHi; checking if the sum of width of each sub-channel CHi is equal to the length of the original channel | 01-08-2015 |
20150249471 | METHOD FOR EARLY TERMINATING DECODING PROCESSES OF SERIAL CONCATENATED CODING AND DECODER USING THE SAME - A method and decoder for early terminating decoding processes of serial concatenated coding are disclosed. The method includes the steps of providing a codeword, encoded by a first coding and a second coding sequentially, decoding of the second coding needing iterative calculations for syndromes; setting a maximum syndrome weight; processing decoding of the second coding for the codeword; terminating decoding of the second coding if a number of the iterative calculations reaches a preset number or a syndrome weight of one iterative calculation is equal to or smaller than the maximum syndrome weight, otherwise repeating step C to step D; and decoding the first coding for the codeword. Time for decoding processes can be reduced since the second coding would not be decoded completed before the decoding processes for the first coding begins. | 09-03-2015 |
20150256199 | DATA FORMAT WITH ECC INFORMATION FOR ON-THE-FLY DECODING DURING DATA TRANSFER AND METHOD FOR FORMING THE DATA FORMAT - A data format with ECC information for on-the-fly decoding during data transfer and method for forming the data format are disclosed. The method includes the steps of: dividing a parity check matrix having a message segment and a parity segment into a plurality of layers; choosing parity bit nodes in the parity segment of a first layer connected to check nodes; assembling the chosen parity bit nodes as a first parity segment and the rest parity bit nodes as a second parity segment; reallocating the parity check matrix so that the first parity segment is on the head of the message segment and the second parity segment is on the end of the message segment; forming a generating matrix according to the reallocated parity check matrix; and operating a message with the generating matrix to obtain the codeword. | 09-10-2015 |
20150256200 | METHOD AND CIRCUIT FOR SHORTENING LATENCY OF CHIEN'S SEARCH ALGORITHM FOR BCH CODEWORDS - A method for shortening latency of Chien's search and related circuit are disclosed. The method includes the steps of: determining a shifted factor, p; receiving a BCH codeword; computing a syndrome from the BCH codeword; finding an error-location polynomial based on the syndrome; and processing Chien's search for the error-location polynomial to find out roots thereof. p is a number of successive zeroes from the first bit of the BCH codeword, the Chien's search starts iterative calculations by substituting a variable of the error-location polynomial with a nonzero element in Galois Field, GF(2 | 09-10-2015 |
20150277857 | SERIAL MULTIPLY ACCUMULATOR FOR GALOIS FIELD - A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost. | 10-01-2015 |
20150318869 | ENCODING AND SYNDROME COMPUTING CO-DESIGN CIRCUIT FOR BCH CODE AND METHOD FOR DECIDING THE SAME - An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of X | 11-05-2015 |
20150349804 | METHOD FOR ENCODING MULTI-MODE OF BCH CODES AND ENCODER THEREOF - A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix. | 12-03-2015 |
20160026435 | SIMPLIFIED INVERSIONLESS BERLEKAMP-MASSEY ALGORITHM FOR BINARY BCH CODE AND CIRCUIT IMPLEMENTING THEREFOR - A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced. | 01-28-2016 |
20160036464 | Multi-Code Chien's Search Circuit for BCH Codes with Various Values of m in GF(2m) - The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2 | 02-04-2016 |
20160077960 | ADAPTIVE COMPRESSION DATA STORING METHOD FOR NON-VOLATILE MEMORIES AND SYSTEM USING THE SAME - An adaptive compression data storing method for non-volatile memories and a system using the method are disclosed. The system includes a host interface unit, a data compressor, a padding unit, a buffer, a combining unit, and a mapping table unit. By combining some compressed data in one page, the present invention can settle the problem that space for storing a compressed data that can not be utilized. Further, lifetime of non-volatile memories can be extended. | 03-17-2016 |
Jui-Pin Hung, Hsinchu TW
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20080295412 | APPARATUS FOR STORING SUBSTRATES - An apparatus includes an enclosure and a door configured to seal the enclosure. The door includes a plate. A rotational apparatus is disposed over the plate. At least one first member with a first arm extends from a first rib of the first member. At least one second member with a second arm extends from a second rib of the second member. The first and second arms are connected to the rotational apparatus. At least one corner member has a first edge. The first edge has a shape corresponding to a shape of a corner of the frame. The corner member is connected to a first end of the third arm. A second end of the third arm is connected to the rotational apparatus. A sealing material is disposed along a first longitudinal side of the first rib and a second longitudinal side of the second rib. | 12-04-2008 |
20080298933 | SUBSTRATE CARRIER, PORT APPARATUS AND FACILITY INTERFACE AND APPARATUS INCLUDING SAME - An apparatus includes a first enclosure, a first door, at least one first valve, at least one inlet diffuser and at least one substrate holder. The first enclosure has a first opening. The first door is configured to seal the first opening. The first valve is coupled to the first enclosure. The inlet diffuser is coupled to the first valve and configured to provide a first gas with a temperature substantially higher than a temperature of an environment around the first enclosure. Each substrate holder disposed within the first enclosure supports at least one substrate. | 12-04-2008 |
20090142903 | CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer. | 06-04-2009 |
20090317214 | NOVEL WAFER'S AMBIANCE CONTROL - A semiconductor manufacturing system, an interface system, a carrier, and a method for providing an ambient controlled environment is disclosed. The semiconductor manufacturing system comprises a plurality of process chambers; at least one interface system, wherein the interface system includes a first ambient control element; at least one carrier, wherein the carrier comprises a second ambient control element; and a control module coupled to the plurality of process chambers, the at least one interface system, and the at least one carrier. | 12-24-2009 |
20110241040 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 10-06-2011 |
20110241061 | HEAT DISSIPATION BY THROUGH SILICON PLUGS - The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip. | 10-06-2011 |
20130157412 | CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer. | 06-20-2013 |
20130168848 | PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING THE SEMICONDUCTOR DEVICE - The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved. | 07-04-2013 |
20130244378 | UNDERFILL CURING METHOD USING CARRIER - A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die. | 09-19-2013 |
20130302979 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS - A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate. | 11-14-2013 |
20130307143 | WAFER-LEVEL PACKAGING MECHANISMS - The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps. | 11-21-2013 |
20140061888 | THREE DIMENSIONAL (3D) FAN-OUT PACKAGING MECHANISMS - The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure. | 03-06-2014 |
20140197535 | WAFER-LEVEL PACKAGING MECHANISMS - A semiconductor package includes a first semiconductor die surrounded by a molding compound. The semiconductor package further includes a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die. The semiconductor package further includes redistribution lines (RDLs) formed over the first conductive pad, wherein at least one RDL of the RDLs extends beyond the boundaries of the semiconductor die, and a portion of the at least one RDL contacts the first conductive pad, wherein a surface of the first conductive pad contacting the portion of the at least one RDL is at a different level than a surface of the molding compound under the at least one RDL extended beyond the boundaries of the first semiconductor die. | 07-17-2014 |
20150017764 | METHOD OF FORMING A SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure. | 01-15-2015 |
20150102503 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A fan out package includes a molding compound, a conductive plug in the molding compound, a dielectric covering the molding compound and a portion of the conductive plug, and an interconnect disposed over the dielectric and contacted with the conductive plug, wherein a width of the interconnect contacting the conductive plug is substantially smaller than a width of the conductive plug in the molding compound, and a width of the interconnect disposed over the dielectric is substantially greater than the width of the conductive plug in the molding compound. | 04-16-2015 |
20150108634 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on the pad, a polymer disposed over the die and patterned to provide a path for the conductive trace passing through, and a molding surrounding the die and the polymer. A top surface of the molding is substantially in a same level as a top surface of the polymer. Further, a method of manufacturing a semiconductor device includes providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening. | 04-23-2015 |
20150137351 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a die, a conductive post disposed adjacent to the die, and a molding surrounding the conductive post and the die, the molding includes a protruded portion protruded from a sidewall of the conductive post and disposed on a top surface of the conductive post. Further, a method of manufacturing a semiconductor device includes disposing a die, disposing a conductive post adjacent to the die, disposing a molding over the conductive post and the die, removing some portions of the molding from a top of the molding, and forming a recess of the molding above a top surface of the conductive post. | 05-21-2015 |
20150147834 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 05-28-2015 |
20150187605 | METHOD OF PACKAGING A SEMICONDUCTOR DEVICE - A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad. | 07-02-2015 |
Jui-Ping Hung, Hsinchu TW
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20120068218 | THERMALLY EFFICIENT PACKAGING FOR A PHOTONIC DEVICE - The present disclosure provides a method of packaging for a photonic device, such as a light-emitting diode device. The packaging includes an insulating structure. The packaging includes first and second conductive structures that each extend through the insulating structure. A substantial area of a bottom surface of the light-emitting diode device is in direct contact with a top surface of the first conductive structure. A top surface of the light-emitting diode device is bonded to the second conductive structure through a bonding wire. | 03-22-2012 |
Jui-Yi Hung, Hsinchu TW
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20090209756 | Emissive transition-metal complexes with both carbon-phosphorus ancillary and chromophoric chelates, synthetic method of preparing the same and phosphorescent organic light emitting diode thereof - The present invention discloses a phosphorescent tris-chelated transition metal complex comprising i) two identical carbon-nitrogen (ĈN) or nitrogen-nitrogen (N̂N) chromophoric ligands being incorporated into a coordination sphere thereof with a transition metal, and one carbon-phosphorus (ĈP) chelate being incorporated into the coordination sphere; or ii) one carbon-nitrogen (ĈN) or nitrogen-nitrogen (N̂N) chromophoric ligand forming a coordination sphere thereof with a transition metal, and two identical carbon-phosphorus (ĈP) chelates being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the chromophoric ligands possess a relatively lower energy gap in comparison with that of the non-chromophoric chelate, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that bright phosphorescence can be observed. The architecture and energy gap of the present molecular designs are suitable for generation of high efficiency blue, green and even red emissions. | 08-20-2009 |
20110204770 | Phosphorescent transition metal complex having a facially arranged carbon-phosphorus-carbon (C+e,cir +0 +ee P+e,cir +0 +ee C) tridentate chelate and organic light emitting diode containing the same - The present invention provides a series of phosphorescent transition metal complexes having a facially arranged, carbon-phosphorus-carbon (ĈP̂C) tridentate chelate, alone with one monoanionic bidentate chromophoric chelate (either ĈN or ÂN) and one arbitrary charge neutral chelate (L), or with one charge neutral bidentate chromophoric chelate (N̂N) and one arbitrary anionic ligand (X); all of them can be used to generate high efficiency photo-induced phosphorescence at room temperature, as well as bright electroluminescence upon employment of these materials in the fabrication of organic light-emitting devices. | 08-25-2011 |
20130005975 | EMISSIVE TRANSITION-METAL COMPLEXES WITH BOTH CARBON-PHOSPHORUS ANCILLARY AND CHROMOPHORIC CHELATES, SYNTHETIC METHOD OF PREPARING THE SAME AND PHOSPHORESCENT ORGANIC LIGHT EMITTING DIODE THEREOF - The present invention provides a phosphorescent tris-chelated transition metal complex having one carbon-nitrogen (ĈN) or nitrogen-nitrogen (N̂N) chromophoric ligand forming a coordination sphere thereof with a transition metal, and two identical carbon-phosphorus (ĈP) chelates being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the chromophoric ligands possess a relatively lower energy gap in comparison with that of the non-chromophoric chelate, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that bright phosphorescence can be observed. The architecture and energy gap of the present molecular designs are suitable for generation of high efficiency blue, green and even red emissions. | 01-03-2013 |
Ju-Pin Hung, Hsinchu TW
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20110081749 | SURFACE MODIFICATION FOR HANDLING WAFER THINNING PROCESS - A wafer is provided with a through via extending a portion of a substrate, an interconnect structure electrically connecting the through via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process. | 04-07-2011 |
Kuei-Chun Hung, Hsinchu TW
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20150055125 | MEASUREMENT METHOD OF OVERLAY MARK - A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark. | 02-26-2015 |
Kun-Chien Hung, Hsinchu TW
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20090067517 | Preamble sequence detection and integral carrier frequency offset estimation method for OFDM/OFDMA wireless communication system - In multi-cell OFDM/OFDMA wireless communication systems, any subscriber station (SS) or mobile station (MS) that intends to enter the system needs to establish time and frequency synchronization with the base station (BS) and obtain the identification code of the BS, where in frequency synchronization one usually needs to estimate the fractional carrier frequency offset (CFO) and the integral CFO. (“Fractional” and “integral” refer to, respectively, the fractional and the integral parts of the ratio of the CFO to subcarrier spacing.) The present invention assumes that the SS or MS first does timing and fractional CFO synchronization and then conducts integral CFO estimation and BS identity detection. The present invention considers integral CFO estimation and BS identity detection jointly, i.e., it proposes solutions that address these topics jointly. The present invention formulates the problem as a signal detection problem in multi-channel interference and obtains the theoretically optimal solution first, and then derives simplified, approximately optimal solutions, in which the present invention employs frequency-domain filtering to calculate the required correlation values which can drastically reduce the high computational complexity of the original theoretically optimal solution but results in little impact on precision. In addition, the present invention proposes several further simplified algorithms, some of which can even eliminate the use of multipliers. The above proposition of frequency-domain filtering has high extensibility in application to related signal sequence detection problems. | 03-12-2009 |
20090232230 | METHOD FOR OFDM AND OFDMA CHANNEL ESTIMATION - This invention discloses a method for OFDM and OFDMA channel estimation via phase-rotated polynomial interpolation and extrapolation (inter/extra-polation). For complexity reason, polynomial inter/extra-polation is an often considered method for channel estimation in orthogonal frequency-division multiplexing (OFDM) and orthogonal frequency-division multiple access (OFDMA) systems, in which the simplest choice is linear inter/extra-polation. But the performance of this method depends on the accuracy of symbol timing estimation as well as the channel delay spread. The invention mitigates the problem by adding a linear phase factor to polynomial inter/extra-polation, which corresponds to adding a delay (also called delay shift) in the time domain. | 09-17-2009 |
Kuo-Chun Hung, Hsinchu TW
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20120281926 | IMAGE FILE PROCESSING METHOD - A processing method for image file includes the following steps. An image file of an image is obtained, in which the image file includes a bit stream and an Exchangeable Image File (EXIF) data. A band indicator and a minimum coded unit (MCU) indicator are read according to an expanded range. A referential DC coefficient is obtained according to a hybrid direct current (DC) coefficient corresponding to a first MCU covered by the expanded range. A sub-clip of the MCU covered by the corresponding expanded range in the bit stream is decoded according to the read band indicator, the MCU indicator and the referential DC coefficient, so as to obtain at least one MCU. | 11-08-2012 |
Kuo-Chung Hung, Hsinchu TW
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20100232079 | SMALL AREA IO CIRCUIT - A small area IO circuit is provided. The IO circuit has one or more parallel circuit unit(s) and an ESD protector set between a core circuit/pre-driver and an IO pad. Each circuit unit includes an off-chip driver and an output resistor, wherein the ESD protector protects ESD event occurred at the IO pad, and the resistor in each circuit unit acts as an ESD block circuit to block ESD current from corresponding off-chip driver. Therefore, transistors in each off-chip driver do not have to be restricted by strict ESD design rules, such that at least a transistor of the off-chip driver(s) is implemented in a single finger layout to lower equivalent capacitance of the off-chip driver(s), and layout areas of the off-chip driver(s) as well as the whole IO circuit can be reduced to achieve a small area IO circuit. | 09-16-2010 |
Kuo-Hsiang Hung, Hsinchu TW
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20120185640 | CONTROLLER AND METHOD FOR CONTROLLING MEMORY AND MEMORY SYSTEM - A memory controller for multiple addressing modes is provided. The memory controller includes a transmitting unit and a control unit. The transmitting unit transmits an identification message to a non-volatile memory. According to whether the non-volatile memory feeds back an acknowledgement message in response to the identification message, the control unit determines an addressing mode to be used for communicating with the non-volatile memory. | 07-19-2012 |
Kuo-Shu Hung, Hsinchu TW
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20100139898 | PRESSURE-ADJUSTABLE MULTI-TUBE SPRAYING DEVICE - A multi-tube spraying device is provided. The multi-tube spraying device includes a body having a closed vessel, wherein a plurality of spraying tubes are disposed in the upper part of the closed vessel and a plurality of heat exchanging tubes are disposed in the lower part of the closed vessel. The device further includes an outlet pipe for discharging refrigerant vapor contained therein and a connecting pipe for introducing the refrigerant vapor from a source to the vessel. In addition, a liquid-vapor separator connected to the refrigerant source separates the refrigerant into vapor and liquid for introducing the liquid refrigerant to the spraying tubes in the vessel while introducing the refrigerant vapor into the vessel. Therefore, a heat exchange is performed between the refrigerant and the heat exchanging tubes. | 06-10-2010 |
20140002715 | ZOOM LENS AND ZOOM LENS MODULE | 01-02-2014 |
Kuo-Tai Hung, Hsinchu TW
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20100261086 | Fuel Cell System and Power Management Method thereof - A fuel cell system and a power management method thereof are provided. The fuel cell system includes a fuel cell power generation part, a switch circuit, a load supply circuit, a status detector, an electronic load circuit, and a control circuit. An input terminal and an output terminal of the switch circuit are respectively coupled to the power generation part and the load supply circuit. The status detector is coupled to a node between the power generation part and the input terminal to detect an output voltage of the power generation part. The electronic load circuit is coupled to a node between the power generation part and the input terminal to perform a current-sinking operation. The control circuit is for generating a first and a second control signals respectively for switching the on-off states of the switch circuit and controlling the current-sinking value of the electronic load circuit. | 10-14-2010 |
Lee Cheng Hung, Hsinchu TW
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20080258813 | Sense Amplifiers Operated Under Hamming Distance Methodology - A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs. | 10-23-2008 |
20100271898 | ACCESS TO MULTI-PORT DEVICES - Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided. | 10-28-2010 |
20110194362 | WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT - A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array. | 08-11-2011 |
Lei-Ken Hung, Hsinchu TW
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20100327769 | Light plate - A light plate includes a light guide plate and four light source modules. The light source modules are disposed around the light guide plate. Each of the light source modules includes a first white light emitting element and a second white light emitting element. The first white light emitting element is capable of emitting a first white beam. The second white light emitting element disposed beside the first white light emitting element is capable of emitting a second white beam. The first white light emitting elements of the light source modules are mirror-symmetrical with respect to a first reference plane and a second reference plane. The second white light emitting elements of the light source modules are mirror-symmetrical with respect to the first reference plane and the second reference plane. The correlated colour temperature (CCT) of the first white beam is greater than the CCT of the second white beam. | 12-30-2010 |
Lien-Yu Hung, Hsinchu TW
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20160061840 | OVARIAN CANCER-SPECIFIC APTAMERS AND APPLICATIONS THEREOF - The present invention provides ovarian cancer-specific aptamers, which are selected in vitro using SELEX and a microfluidic chip system. The aptamers can also bind to different histologically-classified ovarian cancer cells with high affinity accordingly. Therefore, the aptamers of the present invention and the applications thereof can not only be used in detection of ovarian cancer cells but also be applied in recognition of different histologically-classified ovarian cancer cells. | 03-03-2016 |
20160097101 | APTAMER SPECIFIC TO COLORECTAL CANCER CELL AND APPLICATION THEREOF - The present invention provides an aptamer specific to colorectal cancer cells and comprises a nucleotide sequence selected from the group consisting of Seq ID: NO. 1 to Seq ID: NO. 14. The aptamer of the present invention specific to colorectal cancer cell may be applied in colorectal cancer detection and provide a detection method having non-invasive, fast and convenient properties. | 04-07-2016 |
Ming-Che Hung, Hsinchu TW
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20090169188 | Apparatus and method for fan auto-detection - An apparatus for detecting a type of fan and controlling the fan, the fan providing during operation a tachometer signal indicating a speed of the fan, the apparatus includes: a direct current (DC) generator for coupling to the fan and configured to provide a first voltage to the fan; a resistor for providing, while the DC generator provides the first voltage, a sensed voltage relating to the type of the fan, wherein the resistor is connected to a reference voltage and for coupling to a pulse-width modulation (PWM) control terminal of the fan; an input judgment component coupled to the resistor to receive the sensed voltage, the input judgment component being configured to determine whether the fan is a 4-wire PWM fan with an internal pull-up resistor based on the sensed voltage and to provide a judgment signal indicating the determination; a PWM generator coupled to the input judgment component to receive the judgment signal, the PWM generator being configured to provide to the fan a PWM control signal to control the fan if the judgment signal indicates that the fan is the 4-wire PWM fan with an internal pull-up resistor; and a tachometer coupled to the DC generator and the PWM generator, the tachometer being configured to receive the tachometer signal to detect a change in the speed of the fan. | 07-02-2009 |
Ming-Chi Hung, Hsinchu TW
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20090213050 | IMAGE OVER-DRIVING DEVICES AND IMAGE OVER-DRIVING CONTROLLING METHODS - An image over-driving device is provided. An image detection device detects a size and a moving speed of an object according to an image signal and outputs an over-driving control signal according to the detected size and moving speed. A first image register receives and temporarily stores first image data of the image signal in a first frame period, and receives second image data of the image signal and outputs the first image data as a buffer data in a sequential second frame period. A first over-driving unit includes first and second lookup tables recording different over-driving parameters. The first over-driving unit generates first and second over-driving signals according to the buffer data and the second image data respectively by using the first and second lookup tables. The first multiplexer selects the first or second over-driving signal according to the over-driving control signal to drive a display device. | 08-27-2009 |
Ming-Chuan Hung, Hsinchu TW
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20130235447 | ELECTROPHORETIC DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - An electrophoretic display panel includes a driving substrate and an electrophoretic display substrate. The driving substrate includes a first base material, driving electrode patterns, conductive lines, and a shielding layer. The first base material has a first configuration region and a second configuration region. The driving electrode patterns are located inside the first configuration region. The conductive lines are respectively connected to the driving electrode patterns and respectively extend from the first configuration region to the second configuration region. The shielding layer shields the conductive lines and exposes the driving electrode patterns. The electrophoretic display substrate includes a second base material located opposite to the first base material, an electrode layer, and display media. The electrode layer is disposed on the second base material and between the first and second base materials. The display media are disposed between the electrode layer and the driving electrode patterns. | 09-12-2013 |
20140347717 | ELECTROPHORETIC DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - An electrophoretic display panel includes a driving substrate and an electrophoretic display substrate. The driving substrate includes a first base material, driving electrode patterns, conductive lines, and a shielding layer. The first base material has a first configuration region and a second configuration region. The driving electrode patterns are located inside the first configuration region. The conductive lines are respectively connected to the driving electrode patterns and respectively extend from the first configuration region to the second configuration region. The shielding layer shields the conductive lines and exposes the driving electrode patterns. The electrophoretic display substrate includes a second base material located opposite to the first base material, an electrode layer, and display media. The electrode layer is disposed on the second base material and between the first and second base materials. The display media are disposed between the electrode layer and the driving electrode patterns. | 11-27-2014 |
20150262521 | ELECTROPHORETIC DISPLAY APPARATUS AND DRIVING METHOD THEREOF - An electrophoretic display apparatus includes a substrate, a color filter layer, an electrophoretic display film, a common electrode layer, multiple electrode patterns and multiple spacers. The color filter layer is disposed on the substrate and at least includes multiple first color filter patterns and second color filter patterns. The electrophoretic display film is disposed between the substrate and the color filter layer and includes a flexible substrate and multiple display media. The first and second color filter patterns are respectively corresponding to the display media. The electrode patterns at least include multiple first electrode patterns and second electrode patterns. The first electrode patterns receive a first voltage and are disposed respectively correspondingly to the first color filter patterns, while the second electrode patterns receive a second voltage and are disposed respectively correspondingly to the second color filter patterns. The spacers are disposed between the display media and the substrate. | 09-17-2015 |
Ming-Lang Hung, Hsinchu TW
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20120073309 | THERMOELECTRIC DRINKING APPARATUS AND THERMOELECTRIC HEAT PUMP - A thermoelectric drinking apparatus has a feeding pipe, a cooling-gain circulating loop, a heating-gain circulating loop, an outlet pipe, and a thermoelectric heat pump. The thermoelectric heat pump has a cooling unit attached to the cold side of a thermoelectric chip, which has a cooling channel in its interior, and a heating unit attached to the hot side of the thermoelectric chip and provided with a heating channel in its interior. The feeding pipe conducts fluid into the cooling channel and the heating channel respectively. The cooling-gain and heating-gain circulating loop respectively cause fluids in the cooling channel and heating channel to create circular flows, such that the cold side and hot side of the thermoelectric chip respectively cool and heat the fluids via the cooling channel and heating channel. The outlet pipe discharges the cooled and/or heated fluids respectively from the cooling-gain circulating loop and heating-gain circulating loop. | 03-29-2012 |
20150135958 | REGENERATING-TYPE COMPRESSED AIR DRIER AND DEHUMIDIFICATING-AND-REGENERATING UNIT - A regenerating-type compressed air drier for regenerating compressed air by an electrical heating mechanism and a dehumidifying-and-regenerating unit are provided. The drier includes a dehumidifying-and-regenerating unit and an air distribution unit. Compressed high-humidity air and regenerating air are guided to the air distribution unit by a compressed high-humidity air piping and a regenerating air piping. The compressed high-humidity air and the regenerating air are guided to dehumidifying-and-regenerating components of the dehumidifying-and-regenerating unit by a shunt rotor of the air distribution unit to complete the dehumidification of the compressed air and the regeneration of the dehumidifying-and-regenerating components. The drier has a simple structure, and can reduce an undue loss of heat energy by an electrical heating mechanism to the regeneration of the dehumidifying-and-regenerating components. | 05-21-2015 |
20160059182 | DEHUMIDIFYING UNIT, LAYERED TEMPERATURE CONTROL DEHUMIDIFYING ELEMENT AND DRYING DEVICE - A dehumidifying unit, a layered temperature control dehumidifying element and a drying device are provided. The dehumidifying element has a plurality of dehumidifying units. The dehumidifying units are made of a direct heating desorption material and used for dehumidifying air by adsorption and capable of being regenerated by desorption. By performing temperature compensation through a preheater and performing a layered temperature control method on the dehumidifying element, the disclosure achieves a uniform temperature control on the air flow passage of the dehumidifying element so as to improve regeneration performance of the dehumidifying element and reduce energy consumption of the drying device. | 03-03-2016 |
20160059183 | DEHUMIDIFYING UNIT, LAYERED TEMPERATURE CONTROL DEHUMIDIFYING ELEMENT, DRYING DEVICE AND METHOD FOR TEMPERATURE CONTROLLING THE SAME - A dehumidifying unit, a layered temperature control dehumidifying element, a drying device and a temperature control method thereof are provided. The dehumidifying element has a plurality of dehumidifying units. The dehumidifying units are made of a direct heating desorption material and used for dehumidifying air by adsorption and capable of being regenerated by desorption. By performing temperature compensation through a preheater and performing a layered temperature control method on the dehumidifying element, the disclosure achieves a uniform temperature control on the air flow passage of the dehumidifying element so as to improve regeneration performance of the dehumidifying element and reduce energy consumption of the drying device. | 03-03-2016 |
Ming Yu Hung, Hsinchu TW
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20130191818 | PROBABILISTIC POINTER ANALYSIS METHOD USING SSA FORM - A computer-implemented probabilistic pointer analysis method using SSA form comprises the steps of: evaluating a program in an SSA form comprising a target pointer to determine pointer relations between the target pointer, a plurality of aliased pointers related to the target pointer and at least a probable location of the target pointer; and generating a direct probabilistic relation between the target pointer and the at least a probable location of the target pointer according to the pointer relation. | 07-25-2013 |
Min-I Hung, Hsinchu TW
Min-Wei Hung, Hsinchu TW
Patent application number | Description | Published |
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20130265331 | Virtual Reality Telescopic Observation System of Intelligent Electronic Device and Method Thereof - A virtual reality telescopic observation system of an intelligent electronic device. The virtual reality telescopic observation system includes an electronic device arranged for displaying a virtual image, an engagement slot arranged for movably embedding the electronic device therein and a virtual reality telescopic optical module, including at least one optical lens installed corresponding to the electronic device, arranged for projecting the virtual image displayed by the electronic device into the virtual reality telescopic optical module, such that a viewer views the virtual image displayed by the electronic device from the virtual reality telescopic optical module. Wherein, when the viewer performs a virtual reality telescopic observation, the angle, distance and position of the virtual image displayed by the electronic device are adjusted according to a changing of the field of view made by the viewer. | 10-10-2013 |
20150137007 | FLUORESCENCE STRIP, FLUORESCENCE EXCITATION DEVICE AND PORTABLE FLUORESCENCE ANALYSIS SYSTEM WITH THE SAME - A portable fluorescence analysis system comprises a fluorescence strip, a fluorescence excitation device and a mobile Internet device. The fluorescence strip comprises a fluorescence probe configured for detecting an analyte within a specimen. The fluorescence excitation device comprises a sleeve and an excitation light source module. The fluorescence strip is arranged at the one open end of the sleeve. The excitation light source module is arranged at the same opening side of the sleeve and configured for providing an excitation light to excite the fluorescence probe to generate fluorescence. The mobile Internet device comprises an image capturing module and configured for capturing a fluorescence image of the fluorescence strip via the other opening of the sleeve and analyzing fluorescence intensity of the fluorescence image to determine the content of the analyte. The above-mentioned system can be applied to the point of care testing. | 05-21-2015 |
Shao Hsiu Hung, Hsinchu TW
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20090119760 | METHOD FOR RECONFIGURING SECURITY MECHANISM OF A WIRELESS NETWORK AND THE MOBILE NODE AND NETWORK NODE THEREOF - A method for reconfiguring the security mechanism of a wireless network system includes steps of: sending a packet from a network node to a mobile node; sending a negotiation packet from the mobile node to the network node according to a selected authentication protocol; the mobile node and the network node proceeding the authentication process if the received negotiation packet is valid; the mobile node and the network node generating a security association after the authentication process is completed. | 05-07-2009 |
Shao-Kang Hung, Hsinchu TW
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20120037815 | TEM PHASE PLATE LOADING SYSTEM - A phase plate loading system, which can be installed on any commercial TEM (transmission electron microscope) without modifying its optical or lens design, includes an airlock chamber and a transport unit. The airlock chamber is disposed adjacent to the specimen section of the TEM. The transport unit transfers a phase plate into the TEM through the airlock chamber. | 02-16-2012 |
Shao-Lun Hung, Hsinchu TW
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20110310718 | METHOD AND APPARATUS FOR JUDGING BLANK AREA AND DATA RECORDED-AREA OF OPTICAL DISC - An apparatus for judging an optical disc includes a gain controller, an amplitude detecting unit and an amplitude comparing unit. The gain controller is used for receiving a radio frequency signal from an optical pickup head; and processing the radio frequency signal into an amplified radio frequency signal with a target amplitude according to an amplitude feedback signal. The amplitude detecting unit is used for receiving the amplified radio frequency signal, generating the amplitude feedback signal to the gain controller, and outputting a top envelope amplitude according to an top envelope signal of the amplified radio frequency signal. The amplitude comparing unit is used for comparing the top envelope amplitude with a threshold value to generate a resulting signal, and judging whether the laser beams emitted from the optical pickup head are irradiated on a blank area or a data-recorded area according to the resulting signal. | 12-22-2011 |
Sheng-Che Hung, Hsinchu TW
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20090267704 | CAPACITOR DEVICES WITH A FILTER STRUCTURE - A capacitor device is provided. The capacitor device includes at least one capacitor. The capacitor device also includes a first capacitor and a first filter coupling the first capacitor and a conductive region, wherein the first capacitor has a first resonance frequency and the first filter is configured to operate at a first frequency band covering the first resonance frequency. | 10-29-2009 |
Shou-Nan Hung, Hsinchu TW
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20150380112 | MEMORY INTEGRATED CIRCUIT WITH A PAGE REGISTER/STATUS MEMORY CAPABLE OF STORING ONLY A SUBSET OF ROW BLOCKS OF MAIN COLUMN BLOCKS - An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns. | 12-31-2015 |
20160077153 | MEMORY UTILIZING BUNDLE-LEVEL STATUS VALUES AND BUNDLE STATUS CIRCUITS - An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle. | 03-17-2016 |
Shuo-Nan Hung, Hsinchu TW
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20100192039 | MEMORY DEVICE AND OPERATION METHOD THEREOF - A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device. | 07-29-2010 |
20120182804 | ARCHITECTURE FOR A 3D MEMORY ARRAY - Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines. | 07-19-2012 |
20120198298 | On-the-Fly Repair Method for Memory - An on-the-fly repair method for a memory includes: performing a block erase operation on the memory; checking whether the block erase operation is passed or not; finding whether there is any available and healthy redundancy block in the memory if the block erase operation is not passed; programming an address of a failed block to be repaired, an enable bit and at least one error correction bit into both first and second redundancy information regions in a redundancy information set of the memory; checking whether error in the first and the second redundancy information regions is recoverable based on the error correction bit; and if the error is recoverable, then programming the redundancy information set as effective to replace the failed block by the redundancy block related to the effective redundancy information set. | 08-02-2012 |
20130128670 | MEMORY ACCESS METHOD AND FLASH MEMORY USING THE SAME - A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase. | 05-23-2013 |
20130314997 | Memory Access Method and Flash Memory Using the Same - A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase. | 11-28-2013 |
20130343130 | NAND FLASH BIASING OPERATION - A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation. | 12-26-2013 |
20140198576 | PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED MEMORY STRUCTURES - A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set. | 07-17-2014 |
20160064086 | CIRCUIT AND METHOD FOR ADJUSTING SELECT GATE VOLTAGE OF NON-VOLATILE MEMORY - A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well. | 03-03-2016 |
Shuo-Yen Hung, Hsinchu TW
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20080246167 | Layout Structure for Chip Coupling - A layout structure disposed on the substrate of the liquid crystal display (LCD) for chip coupling is provided. The first and second orientations that are substantially perpendicular to the first orientation can be defined on the substrate. The layout structure includes a plurality of lines, which extend along the second orientation, and a plurality of conductive pads that are respectively disposed on the lines. The conductive pads are distributed along the first orientation and staggered along the second orientation. Each line can shift away from the adjacent conductive pad on the first orientation. Thus, the LCD chip has a better conductivity and a thinner dimension under the precision of the conventional machines. | 10-09-2008 |
Ta Chun Hung, Hsinchu TW
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20110049830 | Cycle propelling mechanism - A cycle propelling mechanism includes a rail disposed on a cycle frame, two cranks rotatably coupled to the cycle frame with a main drive shaft, two levers each include one end pivotally coupled to the crank and the other end slidably coupled to the rail for allowing the levers to be moved cyclically relative to the cycle frame, and two foot pedals pivotally attached to the levers for being stepped and operated by user's feet and for allowing the cranks and the lever to be rotated relative to the cycle frame in an elliptical moving stroke and for allowing the foot pedals to be stepped and moved for a longer stepping or moving stroke by the user, and for effectively exercising the more or bigger muscle groups of the user, and for applying bigger power to the cycle propelling mechanism. | 03-03-2011 |
Ta-Kuang Hung, Hsinchu TW
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20110179926 | PROTECTION STRUCTURE FOR CUTTING ELECTRODE STRIP - The present invention discloses a protection structure for cutting an electrode strip, which comprises an electrode strip having at least one cutting channel; and two adhesive tapes respectively stuck to the upper and lower surfaces of the cutting channel, and which can effectively prevent from the formation of burrs and the shattering of solidified compounds in cutting the electrode strips, whereby are promoted the quality, stability and reliability of products. Further, the protection structure for cutting an electrode strip of the present invention also functions as an indicator to identify the cutting site. | 07-28-2011 |
Ted Hung, Hsinchu TW
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20130134080 | NOVEL METHOD FOR TREATING WASTE WATERS - A chemical-free and no-microbe method for pre-treating a broad range of waste waters is presented. The said method involves electrocoagulation (EC) operated in synchronization with electrolytic ozone (EO | 05-30-2013 |
Teng-Hung Hung, Hsinchu TW
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20140055754 | ILLUMINATION SYSTEM, PROJECTION DEVICE AND ILLUMINATION METHOD - An illumination system, a projection device, and an illumination method are provided. The illumination system includes a polarized light source, a polarization switching element, a beam splitting element, a wavelength conversion element, a reflective element, and a wave plate. The polarized light source emits a polarized light beam with a first color. The polarization switching element switches a polarized direction of the polarized light beam at different time points. The beam splitting element separates polarized light beams having different polarized directions. The wavelength conversion element converts the polarized light beam having a first polarized direction to a converted light beam. The reflective element reflects the polarized light beam having a second polarized direction to form a reflected light beam. The beam splitting element combines the converted light beam and the reflected light beam comes from the wave plate disposed between the beam splitting element and the reflective element. | 02-27-2014 |
Tso-Ming Hung, Hsinchu TW
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20130189934 | Radio-Frequency Device, Wireless Communication Device and Method for Enhancing Antenna Isolation - A radio-frequency (RF) device for a wireless communication device includes an antenna disposition area, and a plurality of antennas of a same type, formed in the antenna disposition area by different arrangements, for receiving or transmitting a plurality of wireless signals of a same frequency band. | 07-25-2013 |
Tsung Liang Hung, Hsinchu TW
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20150028819 | METHODS FOR CHARGING A RECHARGEABLE BATTERY - Disclosure has a method for charging a rechargeable battery. The rechargeable battery is charged by a charger in a first constant current mode for a main charge time period. After the main charge time period, the charger stops charging the rechargeable battery for a relaxation time period. During a sample time period that starts after a predetermined settle time period following the beginning of the relaxation time period, the charger detects an open-circuit voltage of the rechargeable battery to compare with a target voltage. If the open-circuit voltage is less than the target voltage, the charger charges the rechargeable battery in a second constant current mode for a coercive charge time period. | 01-29-2015 |
Tsung-Yu Hung, Hsinchu TW
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20080259138 | APPARATUS FOR REGULATING AIR PRESSURE IN INK TANK AND INK-SUPPLYING SYSTEM HAVING THE SAME - The present invention relates to an apparatus ( | 10-23-2008 |
20110012966 | APPARATUS FOR REGULATING AIR PRESSURE IN INK TANK AND INK-SUPPLYING SYSTEM HAVING THE SAME - The present invention relates to an ink-supplying system. The ink-supplying system includes an ink tank for receiving ink therein, a vacuum pump configured for providing a pressure below atmospheric pressure in the ink tank, a first regulating unit, at least one second regulating unit, and a third regulating unit disposed between the vacuum pump and the ink tank, and in communication with each other. The first regulating unit and the third regulating unit each includes a pressure regulating valve and a buffer tank connected therewith, and the at least one second regulating unit comprises a closed-loop pressure regulating valve and a buffer tank connected with the closed-loop pressure regulating valve. | 01-20-2011 |
20110261109 | INKJET PRINTING APPARATUS - An inkjet printing apparatus includes an inkjet print-head, an ink inlet conduit, a vacuum device, and a cleaning assembly. The inkjet print-head defines a number of nozzles. The ink inlet conduit is connected to the inkjet print-head and communicates with the nozzles. The cleaning assembly includes a cleaning member defining a cleaning groove. The vacuum device is connected to the inkjet print-head to impel cleaner received in the cleaning groove to flow through the nozzles along a direction reverse of a direction the ink is jetted. | 10-27-2011 |
Tun-Fu Hung, Hsinchu TW
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20080280430 | METHOD OF FORMING FILMS IN A TRENCH - A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process. | 11-13-2008 |
Tzu-Chien Hung, Hsinchu TW
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20130075779 | LIGHT EMITTING DIODE WITH MULTIPLE TRANSPARENT CONDUCTIVE LAYERS AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a first-type semiconductor layer, an active layer, a second-type semiconductor layer and a transparent, electrically conductive layer formed in sequence. The transparent, electrically conductive layer includes a first transparent, electrically conductive layer on the second-type semiconductor layer and a second transparent, electrically conductive layer on the first transparent, electrically conductive layer. Both the first and second transparent, electrically conductive layers are made of indium tin oxide, while the first transparent, electrically conductive layer has a smaller thickness. During formation of the transparent, electrically conductive layer, a mass flow of introduced oxygen gas to the first transparent conductive layer is lower than that to the second transparent conductive layer. | 03-28-2013 |
20130099254 | LIGHT EMITTING DIODE WITH CHAMFERED TOP PERIPHERAL EDGE - A light emitting diode includes a substrate and a light emitting structure. The light emitting structure includes a light outputting surface away from the substrate and a plurality of sidewalls adjoining the light outputting surface. A top peripheral edge interconnecting the light outputting surface and the sidewalls of the light emitting structure is a rounded top peripheral edge or a beveled top peripheral edge. A top surface of the substrate surrounding the light emitting structure is exposed to air and formed with micro-structures. | 04-25-2013 |
20130175498 | LIGHT EMITTING DIODE - A light emitting diode and a light emitting diode (LED) manufacturing method are disclosed. The LED comprises a substrate; a first n-type GaN layer; a second n-type GaN layer; an active layer; and a p-type GaN layer formed on the substrate in sequence; the second n-type GaN layers has a bottom surface interfacing with the first n-type GaN layer, a rim of the bottom surface has a roughened exposed portion, and Ga-N bonds on the bottom surface has an N-face polarity. | 07-11-2013 |
20130270595 | LIGHT EMITTING DIODE DIE AND LIGHT EMITTING DIODE PACKAGE INCORPORATING THE SAME - An LED die comprises a substrate and an epitaxial layer formed thereon. The epitaxial layer comprises a first n-type semiconductor layer, an active layer and a p-type semiconductor layer grown on the substrate in sequence. The LED die defines a receiving recess formed in a center of a top face of the p-type semiconductor layer. The receiving recess extends through the p-type semiconductor layer, the active layer and into the n-type semiconductor layer along a top-to-bottom direction of the epitaxial layer. A pair of p-pads are located at two opposite sides of the p-type semiconductor layer, respectively. A first n-pad is received in the receiving recess and located on the n-type layer. | 10-17-2013 |
20130280835 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE CHIP - A method for manufacturing a light emitting diode includes providing an epitaxial wafer having a substrate and an epitaxial layer allocated on the substrate. The epitaxial layer comprises a first semiconductor layer, an active layer, a second semiconductor layer sequentially allocated, and at least one blind hole penetrating the second semiconductor layer, the active layer and inside the first semiconductor layer; then a first electrode is formed on the first semiconductor layer inside the at least one blind hole and a second electrode is formed on the second semiconductor layer; thereafter a first supporting layer is allocated on the first electrode and a second supporting layer is allocated on the second electrode. | 10-24-2013 |
20130309795 | METHOD FOR MANUFACTURING LED CHIP WITH INCLINED SIDE SURFACE - A method for manufacturing an LED chip is disclosed wherein a substrate is provided. A first semi-conductor layer is formed on the substrate. A photoresist layer with an inverted truncated cone shape and a blocking layer with an inclined inner surface facing and surrounding the photoresist layer are formed on the first semi-conductor layer. The photoresist layer is removed and an epitaxial region surrounded by the blocking layer is defined. A lighting structure is formed inside the epitaxial region. The blocking layer is then removed and the first semi-conductor layer is exposed. Electrodes are formed and respectively electrically connected to the first semi-conductor layer and the lighting structure. | 11-21-2013 |
20140131725 | LIGHT EMITTING DIODE EPITAXY STRUCTURE - A light emitting diode (LED) epitaxy structure includes an N-type semiconductor layer; an active layer arranged on the N-type semiconductor layer, and a P-type semiconductor layer arranged on the active layer. A horizontal cross-sectional area defined by the active layer is a parallelogram, and none of the internal angles of the parallelogram is a right angle. | 05-15-2014 |
20140138615 | LIGHT EMITTING DIODE - An LED includes a base and an LED die grown on the base. The LED die includes two spaced electrodes and two exposed semiconductor layers. The two electrodes are respectively formed on top surfaces of the two semiconductor layers. At least one of the electrodes extends downwardly from the top surface of the corresponding semiconductor layer along a lateral edge of the LED die to electrically connect an exterior electrode via transparent conducting resin. | 05-22-2014 |
Wei-Cheng Hung, Hsinchu TW
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20130145068 | UNIVERSAL SERIAL BUS DEVICE FOR HIGH-EFFICIENT TRANSMISSION - The present invention discloses a Universal Serial Bus (“USB”) device that includes an Ethernet port configured to receive a first Ethernet packet, and an input control circuit including a data register memory, a header register memory and an input data control circuit. The input data control circuit, upon receiving a first Ethernet packet, stores first packet data of the first Ethernet packet in the data register memory, transmits the first packet data to a USB host, and, in response to the transmission of the first packet data, stores first header data of the first Ethernet packet in the header register memory. | 06-06-2013 |
20130145191 | UNIVERSAL SERIAL BUS DEVICE AND METHOD FOR POWER MANAGEMENT - The present invention discloses a Universal Serial Bus (“USB”) device with a power saving mechanism. The USB device includes an Ethernet physical layer, a USB physical layer, a wakeup packet detection circuit configured to receive a wakeup packet from the Ethernet physical layer, and a standby power saving control circuit. The standby power saving control circuits selects a connection speed from the group including EEE, 10 Mbps, 100 Mbps, 1 Gbps and 10 Gbps, wherein the standby power saving control circuit is able to connect to a wakeup device at the selected connection speed, so that the USB system can enter an optimal power saving status while in a standby mode. The connection speeds are defined in the specification of IEEE 802.3az as 10BASE-T, 100BASE-TX, 1000BASE-T, 10GBASE-T, 1000BASE-KX, 10GBASE-KX4, 10GBASE-KR. | 06-06-2013 |
Wen-Chen Hung, Hsinchu TW
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20130146911 | LIGHT EMITTING DIODE PACKAGE AND LENS MODULE USED THEREIN - An LED package includes an LED die and a lens module. The lens module covers the LED die. Light emitted from the LED die travels through the lens module. The lens module includes a concave lens and a convex lens with a smaller radial dimension than that of the concave lens. The concave lens covers the LED die. The convex lens is attached on a center of a surface of the concave lens away from the LED die. Optical axes of the concave lens and the convex lens are both collinear with a central axis of the LED die. Light from the LED die is diverged by the lens module to a peripheral side of the LED package. | 06-13-2013 |
Wensen Hung, Hsinchu TW
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20120169367 | HIGH FREQUENCY PROBING STRUCTURE - The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board. | 07-05-2012 |
Wolf Hung, Hsinchu TW
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20140273459 | Systems and Methods for a Narrow Band High Transmittance Interference Filter - The present disclosure provides an interference filter, a lithography system incorporating an interference filter, and a method of fabricating an interference filter. The interference filter includes a transparent substrate having a front surface and a back surface, a plurality of alternating material layers formed over the front surface of the transparent substrate that form a bandpass filter, and an anti-reflective structure formed over the back surface of the transparent substrate. The alternating material layers alternate between a relatively high refractive index material and a relatively low refractive index material. | 09-18-2014 |
Yen-Hsiang Hung, Hsinchu TW
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20090251667 | Projector and color adjusting method thereof - A color adjusting method is applied to a projector. The projector has a light emitting element and a color wheel. The light emitting element supplies light, and makes the light pass through the color wheel so as to generate a plurality of different color lights. These different color lights are used to form a color image. The color adjusting method includes the steps of providing a plurality of driving waveforms which is dynamically switched for driving the light emitting element; defining a major color light of the color image, which is selected from the different color lights; and switching to one of these driving waveforms when the major color light is generated by the light passing through the color wheel. Thus, the light energy of the major color light is enhanced by means of driving the light emitting element through the switched driving waveform. | 10-08-2009 |
Yi-Feng Hung, Hsinchu TW
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20150106135 | BOOKING DECISION METHOD FOR TRANSPORTATION INDUSTRY BY SAMPLING OPTIMAL REVENUE - In a booking decision method for transportation industry by sampling optimal revenues, a random sample scenario of a scenario index is generated. A first optimal revenue is generated under a condition of rejecting the current arrival booking request, and a second optimal revenue is generated under a condition of accepting the current arrival booking request. The scenario index is increased by 1 if the sample scenario index is smaller than a total number of sample scenarios; otherwise, a first average revenue of the first optimal revenue and a second average revenue of the second optimal revenue are calculated, and the marginal profit is calculated according to the first average revenue and the second average revenue. If the price of a current arrival request is greater than or equal to the marginal profit, the current arrival booking request is accepted; otherwise, the current arrival booking request is rejected. | 04-16-2015 |
Yi-Hsuan Hung, Hsinchu TW
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20090150016 | VEHICLE HYBRID POWER SYSTEM AND METHOD FOR CREATING SIMULATED EQUIVALENT FUEL CONSUMPTION MULTIDIMENSIONAL DATA APPLICABLE THERETO - A vehicle hybrid power system is provided according to the present invention. The hybrid power system is characterized by applying the concept of minimum equivalent fuel consumption, and then simulating equivalent fuel consumptions based on respective energy consumption or increase of motor and generator of a motor vehicle, and also defining simulated equivalent fuel consumption formula and making a list of system state parameters, system control parameters, and system negative load parameters, thereby obtaining simulated equivalent fuel consumption multidimensional data by entering the system parameters derived from a discretization/transformation process in the defined simulated equivalent fuel consumption formula; wherein, the simulated equivalent fuel consumption multidimensional data are revised to comprise subsystems, such as system engine, motor, generator, and others to determine a system control strategy of holistic optimization, thereby achieving the objective of saving energy. The present invention further provides a method for creating simulated equivalent fuel consumption multidimensional data, which is applicable to the hybrid power system of the present invention. | 06-11-2009 |
Ying-Chan Hung, Hsinchu TW
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20150093840 | ENZYME-FREE COLORIMETRIC IMMUNOASSAY - A colorimetric immunoassay of the present invention uses nanostructured material with high absorption and high scattering ability as a label material for biosensors. Subject matters to be measured may be characterized or quantified by determining the changes in optical properties of the nanostructured material. The biosensor of the present invention may be operated in broad light wavelength range and detected by direct observation with naked eye. The biosensor of the present invention may be also provided with advantages such as higher sensitivity and lower cost. | 04-02-2015 |
Yung-Tai Hung, Hsinchu TW
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20090023289 | CONDUCTOR REMOVAL PROCESS - A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns. | 01-22-2009 |
20100244180 | METHOD FOR FABRICATING DEVICE ISOLATION STRUCTURE - A method of a fabricating a semiconductor device includes providing a substrate having a first region and a second region. A pad layer is formed overlying the substrate in both the first region and the second region. A mask layer is then formed overlying the pad layer. Thereafter, the mask layer, the pad layer and the substrate are patterned to form a plurality of first trenches in the first region and a plurality of second trenches in the second region. A trimming process is then performed on the mask layer to remove a portion of the mask layer. An insulation layer is formed over the substrate and fills the plurality of the first trenches and the plurality of the second trenches. Ultimately, a planarization process is performed on the insulation layer. | 09-30-2010 |
20150187595 | A SEMICONDUCTOR DEVICE COMPRISING A SURFACE PORTION IMPLANTED WITH NITROGEN AND FLUORINE - A method of fabricating a semiconductor device is provided. A substrate is provided. Thereafter, a dielectric layer is formed on the substrate, wherein the dielectric layer includes a first portion adjacent to the substrate and a second portion adjacent to the first portion. Afterwards, the dielectric layer is treated with nitrogen trifluoride (NF | 07-02-2015 |
Yung-Ti Hung, Hsinchu TW
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20150117135 | SLURRY FEED SYSTEM AND METHOD OF PROVIDING SLURRY TO CHEMICAL MECHANICAL PLANARIZATION STATION - A slurry feed system includes a valve manifold, a mixing tank, a slurry feed pump, a surface tension meter and suction piping, discharge piping as well as slurry return piping. The valve manifold includes inlet piping, outlet piping fluidly coupled to the inlet piping, and a slurry discharge header for supplying slurry to CMP stations. The slurry feed pump is connected to the mixing tank by the suction piping. The discharge piping is routed from the slurry feed pump to the inlet piping of the valve manifold. The slurry return piping is routed from the outlet piping of the valve manifold to the mixing tank. The suction piping, the discharge piping, the inlet piping, the outlet piping and the slurry return piping define a first slurry supply loop. The surface tension meter is coupled to the first slurry supply loop. | 04-30-2015 |
Yu-Wei Hung, Hsinchu TW
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20120330441 | CONTROL SYSTEM AND CONTROL METHOD FOR IDENTIFYING CORRESPONDING POSITION - The disclosed exemplary embodiments relates to a control system and a control method for identifying corresponding position. The control system includes a plurality of electronic control modules, each electronic control module having a microcontroller electrically coupled to at least one joint, and the joint is configured for connecting to a joint of neighboring electronic control module. The electronic control modules include a main-control-terminal electronic control module, an assembling electronic control module and at least one detecting electronic control module. The main-control-terminal electronic control module is configured for assigning one of the electronic control modules to be the assembling electronic control module, and assigning the rest of the electronic control modules to be the detecting electronic control module. The assembling electronic control module is configured for obtaining an identifying signal of the neighboring electronic control module so as to recognize the corresponding position of the electronic control modules. | 12-27-2012 |
Zi-Shun Hung, Hsinchu TW
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20110071112 | Compositions and Methods for Preserving Colors and Patterns of Plants - The present invention relates to a composition for preserving plants, which comprises 5 carbon alcohol, at least one alcohol selected from the group consisting of 3 carbon alcohol and 4 carbon alcohol, a thiourea and at least one acid selected from the group consisting of tartaric acid and boric acid. The composition is used to preserve colors, patterns and DNA of plants. The composition can also be used to change colors of flowers. The present invention also relates to a method for preserving plants, which comprises soaking the plants in the composition of the present invention. | 03-24-2011 |