Patent application number | Description | Published |
20080315308 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE AND METHOD OF FABRICATING THE SAME - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 12-25-2008 |
20110204441 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 08-25-2011 |
20130277725 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate, a well region in the substrate, a patterned first dielectric layer on the substrate extending over the well region, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure includes a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, the first section and the second section intersecting each other in a cross pattern. The patterned second gate structure includes at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 10-24-2013 |
20140266409 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region. | 09-18-2014 |
20150118820 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure with a high voltage area and a low voltage area is provided. The method includes the following steps: providing a substrate of a first conductivity type; forming a second doped region of a second conductivity type in the substrate by a first implantation; forming a first doped region of a first conductivity type in the second doped region by a second implantation; forming an insulating layer on the substrate; forming a resistor on the insulating layer, wherein the resistor is electrically connecting the high voltage area and the low voltage area; and forming a conductor electrically connected to the resistor. The step of forming a first doped region defines the high voltage area and the low voltage area. | 04-30-2015 |
Patent application number | Description | Published |
20090256183 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
20090256184 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
20110121373 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 05-26-2011 |
20110140201 | LATERAL POWER MOSFET STRUCTURE AND METHOD OF MANUFACTURE - A lateral power MOSFET with a low specific on-resistance is described. Stacked P-top and N-grade regions in patterns of articulated circular arcs separate the source and drain of the transistor. | 06-16-2011 |
20110169137 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes. | 07-14-2011 |
20110266601 | Single Gate Semiconductor Device - A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor. | 11-03-2011 |
20120025352 | BIPOLAR JUNCTION TRANSISTOR DEVICES - A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other. | 02-02-2012 |
20120241861 | Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer. | 09-27-2012 |
20120280316 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 11-08-2012 |
20130020680 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion. | 01-24-2013 |
20130207191 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region and a second doped region. The first doped region comprises a first contact region. The first doped region and the first contact region have a first type conductivity. The second doped region comprises a second contact region. The second doped region and the second contact region have a second type conductivity opposite to the first type conductivity. The first doped region is adjacent to the second doped region. | 08-15-2013 |
20130221404 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall. | 08-29-2013 |
20130265102 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type formed in the deep well and extending down from the surface of the substrate; and a second well having the second conductive type formed in the deep well and extending down from the surface of the substrate, and the second well adjacent to the first well. The first well includes a block region and plural finger regions joined to one side of the block region, while the second well includes plural channel regions interlaced with the finger regions to separate the finger regions. | 10-10-2013 |
20130295728 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 11-07-2013 |
20140024205 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion. | 01-23-2014 |
20140054656 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure. | 02-27-2014 |
20140065781 | Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer. | 03-06-2014 |
20140264336 | PATTERN FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICE MANUFACTURING AND PROCESS MONITORING - A pattern for use in the manufacture of semiconductor devices is provided which, according to an example embodiment, may comprise at least one second field region comprising a main array of dies, each having a height of Y | 09-18-2014 |
20140342511 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall. | 11-20-2014 |
20150214361 | Semiconductor Device Having Partial Insulation Structure And Method Of Fabricating Same - A method for fabricating a semiconductor device includes providing a substrate having a first conductive type, forming a high-voltage well having a second conductive type in the substrate, forming a drift region in the high-voltage well, and forming an insulation layer on the substrate. The insulation layer includes a first insulation portion and a second insulation portion respectively covering opposite edge portions of the drift region, and not covering a top portion of the drift region. | 07-30-2015 |
20160043180 | SEMICONDUCTOR DEVICE INCLUDING HIGH-VOLTAGE DIODE - A semiconductor device includes a substrate, a high-voltage N-well (HVNW) disposed in the substrate, a bulk P-well disposed in the substrate and adjacent to an edge of the HVNW, a high-voltage (HV) diode disposed in the HVNW, the HV diode including a HV diode P-well disposed in the HVNW and spaced apart from the edge of the HVNW, and an N-well disposed in the HVNW and between the HV diode P-well and the bulk P-well. A doping concentration of the N-well is higher than a doping concentration of the HVNW. | 02-11-2016 |
Patent application number | Description | Published |
20090026861 | GENERATOR FOR EXERCISE EQUIPMENT - A generator for exercise equipment includes a disc and a case. The case has a surface. A number of first locating holes are disposed on the surface to accommodate coils therein. The case is pivotally connected to the disc. The case has an inner wall. A number of second locating holes are disposed on the inner wall of the case to accommodate magnets therein. By spinning, the disc is spinning with respect to the case so that the electricity is generated thereafter. | 01-29-2009 |
20140046314 | ELECTROMAGNETIC THERMOTHERAPY NEEDLE - An electromagnetic thermotherapy needle includes a needle body, a covering element, and a holding portion. The material of the needle body includes a magnetically susceptible material. The needle body is formed integrally as one piece and includes a front portion and a rear portion. The front portion has a tip end, and a radial width of the front portion is larger than that of the rear portion. The covering element covers the rear portion, and includes a magnetically non-susceptible material. The holding portion is connected with the covering element or the needle body. | 02-13-2014 |
20140081069 | DEEP MAGNETIC FIELD GENERATING APPARATUS - A deep magnetic field generating apparatus includes a first coil unit and a second coil unit. The second coil unit is connected with the first coil unit, and disposed around the first coil unit horizontally. Accordingly, the deep magnetic field generating apparatus can generate a desired deep magnetic field. | 03-20-2014 |
20150233749 | METHOD AND DEVICE FOR DETECTING ABNORMAL STATE OF MEDICAL CONTAINER - A method for detecting abnormal state of medical container contains steps of: enabling a weight detecting unit to detect weight of a medical container which is coupled with a patient to acquire content change data; enabling an inclination detecting unit to detect inclination state of the medical container to acquire inclination data; receiving the content change data and the inclination data by a controlling unit; and comparing the content change data and the inclination data with preset content data and initial inclination data respectively, such that when the content change data is different from the preset content data, a warning unit is started by the controlling unit; or when the inclination data is different from the initial inclination data, the warning unit is started by the controlling unit. In addition, a device for detecting abnormal state of the medical container matches is used to execute above-mentioned steps. | 08-20-2015 |
20150366439 | METHOD OF OPERATING AN ENDOSCOPE BY CHANGING MAGNETIC FIELD AND CONTROLLING FEEDING AND ROTATION OF THE ENDOSCOPE SYNCHRONOUSLY - A method of operating an endoscope by changing a magnetic field and controlling a feeding and a rotation synchronously comprises steps of: providing an endoscope, the endoscope including a magnetic section formed on a front end thereof, the magnetic section having a multi-section bending portion and a magnetic element; and setting a target position in a space. The method of operating the endoscope further comprises steps of: exerting a magnetic field on the magnetic element of the magnetic section, any one of a size, a direction, and a position of the magnetic field is allowed to be changed after exerting the magnetic field on the magnetic element of the magnetic section so that the magnetic element is guided by the magnetic field; and controlling the endoscope to feed or/and rotate based on the target position and a bendable direction of the multi-section bending portion. | 12-24-2015 |
Patent application number | Description | Published |
20090317837 | CANCER DIAGNOSIS BASED ON LEVELS OF ANTIBODIES AGAINST GLOBO H AND ITS FRAGMENTS - A cancer diagnostic method using a glycan array that contains Gb5 and Globo H, Bb2, Bb3, and/or Bb4. | 12-24-2009 |
20100247571 | METHODS AND COMPOSITIONS FOR IMMUNIZATION AGAINST VIRUS - Immunogenic compositions comprising partially glycosylated viral glycoproteins for use as vaccines against viruses are provided. Vaccines formulated using mono-, di-, or tri-glycosylated viral surface glycoproteins and polypeptides provide potent and broad protection against viruses, even across strains. Pharmaceutical compositions comprising monoglycosylated hemagglutinin polypeptides and vaccines generated therefrom and methods of their use for prophylaxis or treatment of viral infections are disclosed. Methods and compositions are disclosed for influenza virus HA, NA and M2, RSV proteins F, G and SH, Dengue virus glycoproteins M or E, hepatitis C virus glycoprotein E1 or E2 and HIV glycoproteins gp120 and gp41. | 09-30-2010 |
20150328299 | VACCINES WITH HIGHER CARBOHYDRATE ANTIGEN DENSITY AND NOVEL SAPONIN ADJUVANT - The present invention provides vaccines comprising carbohydrate antigen conjugated to a diphtheria toxin (DT) as a carrier protein, wherein the ratio of the number of carbohydrate antigen molecule to the carrier protein molecule is higher than 5:1. Also disclosed herein is a novel saponin adjuvant and methods to inhibit cancer cells, by administering an effective amount of the vaccine disclose herein. | 11-19-2015 |
20150335728 | METHODS AND COMPOSITIONS FOR IMMUNIZATION AGAINST VIRUS - Immunogenic compositions comprising partially glycosylated viral glycoproteins for use as vaccines against viruses are provided. Vaccines formulated using mono-, di-, or tri-glycosylated viral surface glycoproteins and polypeptides provide potent and broad protection against viruses, even across strains. Pharmaceutical compositions comprising monoglycosylated hemagglutinin polypeptides and vaccines generated therefrom and methods of their use for prophylaxis or treatment of viral infections are disclosed. Methods and compositions are disclosed for influenza virus HA, NA and M2, RSV proteins F, G and SH, Dengue virus glycoproteins M or E, hepatitis C virus glycoprotein E1 or E2 and HIV glycoproteins gp120 and gp41. | 11-26-2015 |