Patent application number | Description | Published |
20120089770 | FLASH MEMORY DEVICES WITH HIGH DATA TRANSMISSION RATES AND MEMORY SYSTEMS INCLUDING SUCH FLASH MEMORY DEVICES - A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode. | 04-12-2012 |
20160005482 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 01-07-2016 |
20160005483 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 01-07-2016 |
20160005484 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 01-07-2016 |