Patent application number | Description | Published |
20090057731 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a MOS transistor, a structure of trenches or fins arranged in parallel to a gate length direction is formed in a stepwise manner along a gate width direction to thereby reduce a step height of each step. Even if the MOS transistor includes a deep trench or a high fin in order to increase driving performance per unit area, a uniform impurity concentration in a channel region, a source diffusion layer, and a drain diffusion layer can be made by an ion implantation method. Accordingly, there can be obtained a stable characteristic that variation in the characteristic due to a surface on which the channel is formed does not appear, and a lateral MOS transistor with high driving performance having a reduced on-resistance per unit area can be provided. | 03-05-2009 |
20090206439 | Semiconductor device - In order to provide an ESD protection circuit having high immunity to ESD destruction without increasing a chip area of a semiconductor device, a diode-type ESD protection circuit formed of a junction between a first conductivity type diffusion layer and a second conductivity type diffusion layer is formed in an entire peripheral region or a part of the peripheral region outside of internal circuits and bonding pads of the chip, and a diffusion layer formed to fix a substrate potential of the chip and electrically connected to a power source or a ground provided in the peripheral region of the chip is used for any one of the first conductivity type diffusion layer and the second conductivity type diffusion layer, permitting enlargement of the size of the ESD protection circuit without increasing a chip area, and enhancement of immunity to ESD destruction of the semiconductor device. | 08-20-2009 |
20090212361 | Semiconductor device and method of manufacturing the same - A LOCOS offset type MOS transistor includes a MOS transistor including: a gate electrode formed on a gate oxide film, the gate oxide film being formed on a surface of a semiconductor substrate of a first conductivity type; a LOCOS oxide film and a first offset diffusion layer of a second conductivity type, which are formed on the surface of the semiconductor substrate at one of both sides and only one side of the gate electrode, a part of a region of the LOCOS oxide film, which is not an end of the LOCOS oxide film, being removed; and one of both of a source diffusion layer and a drain diffusion layer of the second conductivity type and only a drain diffusion layer of the second conductivity type is formed in the first offset diffusion layer corresponding to the region in which the LOCOS oxide film is removed. Accordingly, a semiconductor device may be provided including the MOS transistor which has a high break down voltage and ensures a proper operation even at a voltage of 50 V or higher by covering a region in which electric field accumulation is caused below the drain diffusion layer with the offset diffusion layer. | 08-27-2009 |
20090212375 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 08-27-2009 |
20100025764 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed. | 02-04-2010 |
20100032676 | Semiconductor integrated circuit device and a manufacturing method for the same - Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design. | 02-11-2010 |
20110039392 | SEMICONDUCTOR DEVICE WITH RESISTOR AND FUSE AND METHOD OF MANUFACTURING THE SAME - A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on the resistor in the cutting of the fuse element, has a small contact resistance occurred between elements, and has stable characteristics, and a method of manufacturing the same. | 02-17-2011 |
20110068412 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer. | 03-24-2011 |
20110156138 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 06-30-2011 |
20110227192 | Semiconductor device and method of manufacturing the same - Provided are a semiconductor device including a highly precise resistor formed of a polycrystalline silicon film and a method of manufacturing the same, in which: a portion of a base insulating film below a portion of the polycrystalline silicon film which becomes a resistance region into a convex shape; and the polycrystalline silicon film which becomes the resistor is selectively formed into a thin film, while an electrode lead-out region remains thick so as to obtain the resistor with high precision, high resistivity, and a preferable temperature coefficient while preventing penetration in an opening for contact. | 09-22-2011 |
20120256251 | SEMICONDUCTOR DEVICE - An ESD protection element is disclosed in which LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to maintain an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again. | 10-11-2012 |
20130026995 | BATTERY PROTECTION IC AND BATTERY DEVICE - Provided are a battery protection IC and a battery device, which are capable of ensuring safety even when a charger is connected in a reverse direction. The battery protection IC includes a first switch element provided between an overcurrent detection terminal and a VDD terminal so that, when the charger is connected with reverse polarity, the first switch element interrupts a current path between the overcurrent detection terminal and the VDD terminal. The battery protection IC further includes a second switch element provided between a charge control terminal and the VDD terminal so that, when the charger is connected with reverse polarity, the second switch element interrupts a current path between the charge control terminal and the VDD terminal. | 01-31-2013 |