Patent application number | Description | Published |
20090123006 | MULTI-MODE SOUND REPRODUCTION SYSTEM AND A CORRESPONDING METHOD THEREOF - There is provided a multi-mode sound reproduction system for reproduction of both stereophonic signals and multi-channel audio signals. The system includes a first pair of speakers positioned on a left portion of a user, the user being at a pre-determined facing, the first pair of speakers comprising a first primary speaker which is stackable with a first secondary speaker; a second pair of speakers positioned on a right portion of the user, the user being at the pre-determined facing, the second pair of speakers comprising a second primary speaker which is stackable with a second secondary speaker. The system may preferably include an arrangement of electronic components for controlling output of audio signals from the first pair and the second pair of speakers. It is preferable that in a first mode with the first and second pair of speakers in an unstacked configuration, the signals do not pass through the arrangement of electronic components prior to output. It is also preferable that in a second mode with each of the first and second pair of speakers in a stacked configuration, the arrangement of electronic components allows either stereophonic signals or multi-channel audio signals to be separately processed and reproduced in the first pair and the second pair of speakers. A corresponding method is also disclosed. | 05-14-2009 |
20100217411 | METHODS AND AN APPARATUS FOR OPTIMIZING PLAYBACK OF MEDIA CONTENT FROM A DIGITAL HANDHELD DEVICE - There is provided an apparatus and methods for optimizing playback of media content from a digital handheld device. The apparatus may be functionally connected to the digital handheld device, and for allowing placement of the digital handheld device at a receptor. Correspondingly, the methods for optimizing playback of media content from a digital handheld device preferably entail a usage of the aforementioned apparatus. | 08-26-2010 |
20110218658 | SYSTEM FOR REPRODUCTION OF MEDIA CONTENT - There is provided a system for reproduction of media content. The system includes at least one sound reproduction apparatus being wirelessly connectable to at least one control apparatus via at least one data channel, the at least one control apparatus being connected to the at least one sound reproduction apparatus once the at least one control apparatus receives a first signal indicating a presence of the at least one sound reproduction apparatus; and the at least one control apparatus being wirelessly connectable to at least one data storage apparatus on a data network. Preferably, the at least one sound reproduction apparatus plays back audio signals of the media content which is either stored on the at least one control apparatus or received via the data network, and with the audio signals of the media content being received at a memory module of the at least one sound reproduction apparatus. The audio signals may be played back either in a streaming form or a stored-data playback form, the form depending on the audio signals stored in the memory module. | 09-08-2011 |
20120148075 | METHOD FOR OPTIMIZING REPRODUCTION OF AUDIO SIGNALS FROM AN APPARATUS FOR AUDIO REPRODUCTION - There is provided a method for optimizing reproduction of audio signals from an apparatus for audio reproduction with the apparatus for audio reproduction having a variable number of speakers. The method includes determining performance characteristics of each of the variable number of speakers; comparing performance characteristics of each of the variable number of speakers with each other; and designating a master speaker from the variable number of speakers either with or without manual intervention. | 06-14-2012 |
20130051572 | METHOD FOR OPTIMIZING REPRODUCTION OF AUDIO SIGNALS FROM AN APPARATUS FOR AUDIO REPRODUCTION - There is provided a calibration method for calibrating a variable number of speakers. The method includes determining physical features around a location of each of the variable number of speakers and calibrating at least one of the variable number of speakers. | 02-28-2013 |
Patent application number | Description | Published |
20120112803 | PROCESS, TEMPERATURE, PART AND SETTING INDEPENDENT RESET PULSE ENCODING AND DECODING SCHEME - A method of generating a reset signal for an integrated circuit without a dedicated reset pin includes calibrating a first clock pulse from a clock signal, measuring a second clock pulse from the clock signal, measuring a third clock pulse from the clock signal, and generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within an expected first value range, and if the third clock pulse is within an expected second value range. | 05-10-2012 |
20120133391 | CIRCUIT AND METHOD FOR ADDING DITHER TO VERTICAL DROOP COMPENSATION USING LINEAR FEEDBACK SHIFT REGISTERS - Vertical dithering is performed for vertical droop compensation in image processing using Linear Feedback Shift Registers (LFSRs). Line memories are not used. A compensation circuit includes a signature reload input signal coupled to the input of five LFSRs. Each LFSR includes a signature store. The output of each LFSR provides a sequence output signal that is gated with a corresponding enable signal in a first logic circuit. The output of all of the first logic circuits are combined in a second logic circuit to provide a control signal output. | 05-31-2012 |
20120155588 | CLOCK RESYNCHRONIZATION CIRCUIT AND METHOD - A control circuit receives a first clock signal at a first frequency, a frequency division signal specifying a divisor number, and a second clock signal at a second frequency (higher than the first frequency). The control circuit includes a phase control block that defines non-overlapping portions of a pulse of the second clock to include center, left and right portions. A determination is then made as to whether an edge of the first clock is located within the center portion. In response to such a determination, a number of periods of the second clock signal which occur within one or more periods of the first clock signal is compared to a number derived from the divisor number to generate a frequency selection signal indicative of that comparison. A controlled oscillator circuit generates the second clock signal at the second frequency, wherein the second frequency is specified by the frequency selection signal. To the extent the edge of the first clock is located within either the left or right portions, phase adjustment is made to move the edge towards the center portion. | 06-21-2012 |
20130002316 | RESET PULSE ENCODING AND DECODING SCHEME WITH NO INTERNAL CLOCK - An integrated circuit (IC) provides a reset function. The IC receives a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal and provides a reset function when it is determined that the command is received. A device including the IC and a system including the device are provided. | 01-03-2013 |
20150015317 | SPARE CELL STRATEGY USING FLIP-FLOP CELLS - Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells. | 01-15-2015 |
20150039956 | TEST MUX FLIP-FLOP CELL FOR REDUCED SCAN SHIFT AND FUNCTIONAL SWITCHING POWER CONSUMPTION - A new flip-flop cell that is more efficient in scan chain configuration includes a multiplexer, storage element (e.g., a flip-flop), an inverter, and multiple logic gates. The flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode. In capture mode, the data input signal is passed to the storage element, and the internal outputs of the flip-flop are supplied to the logic gates. Based on the internal outputs and scan enable signal, the logic gates disable either one of two outputs of the flip-flop cell. In capture mode, a test flip-flop cell output is disabled. In scan shift mode, a standard function flip-flop cell output is disabled. | 02-05-2015 |
Patent application number | Description | Published |
20090023431 | Systems and Methods for Communicating with a Network Switch - Systems and methods for communicating with a network device are provided. In this regard, a representative system, among others, includes a network switch associated with a telecommunications device; and a wireless interface device that wirelessly communicates with the network switch, the wireless interface device being configured to obtain information associated with the network switch and display at least a portion of the information obtained on a display device. A representative method, among others, for communicating with a network switch includes establishing a wireless link between the network switch and a wireless interface device; obtaining information associated with the network switch by the wireless interface device via the wireless link; and displaying at least a portion of the information obtained on a display device of the wireless interface device. | 01-22-2009 |
20100095145 | SYSTEM FOR REDUCING POWER CONSUMPTION IN AN ELECTRONIC CHIP - A system for reducing power consumption in an electronic device comprising at least one electronic chip comprises a plurality of local access network (LAN) ports, a transceiver coupled between the LAN ports and the electronic chip, a PLA device, and a central processing unit (CPU). The CPU is configured to power off the electronic chip in response to a period of inactivity on the LAN ports and power on the electronic chip in response to a signal from the PLA device. | 04-15-2010 |
20120096296 | SYSTEM FOR REDUCING POWER CONSUMPTION IN AN ELECTRONIC CHIP - A system for reducing power consumption in an electronic device comprising at least one electronic chip comprises a plurality of local access network (LAN) ports, a transceiver coupled between the LAN ports and the electronic chip, a PLA device, and a central processing unit (CPU). The CPU is configured to power off the electronic chip in response to a period of inactivity on the LAN ports and power on the electronic chip in response to a signal from the PLA device. | 04-19-2012 |
20130277818 | CHIP CARRIER SUPPORT SYSTEMS - In one embodiment, a chip carrier support system includes a chip carrier support structure and a chip carrier. The chip carder forms a complementary fit with the chip carder support structure and includes an integrated circuit and a plurality of leads in communication with the integrated circuit. | 10-24-2013 |
Patent application number | Description | Published |
20090032975 | Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution - A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer. | 02-05-2009 |
20100308443 | Semiconductor Device and Method of Forming an Interconnect Structure with TSV Using Encapsulant for Structural Support - A semiconductor device has a conductive via formed through in a first side of the substrate. A first interconnect structure is formed over the first side of the substrate. A semiconductor die or component is mounted to the first interconnect structure. An encapsulant is deposited over the first interconnect structure and semiconductor die or component. A portion of a second side of the substrate is removed to reduce its thickness and expose the TSV. A second interconnect structure is formed over the second side of the substrate. The encapsulant provides structural support while removing the portion of the second side of the substrate. The second interconnect structure is electrically connected to the conductive via. The second interconnect structure can include a redistribution layer to extend the conductivity of the conductive via. The semiconductor device is mounted to a printed circuit board through the second interconnect structure. | 12-09-2010 |
20110012258 | Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface - A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking. | 01-20-2011 |
20110108970 | SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER AND METHOD OF MANUFACTURE THEREOF - A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed. | 05-12-2011 |
20110210436 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; attaching a base barrier on the base substrate adjacent a base perimeter thereof; mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier. | 09-01-2011 |
20120013004 | Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support - A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer. | 01-19-2012 |
20120061854 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; mounting a bottom integrated circuit over the bottom substrate; mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate; connecting a top interconnect between the bottom substrate and the top substrate; and forming an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit. | 03-15-2012 |
20120068328 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ACTIVE SURFACE HEAT REMOVAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side. | 03-22-2012 |
20120074560 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier. | 03-29-2012 |
20120074588 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier. | 03-29-2012 |
20120112340 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 05-10-2012 |
20120187568 | Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants - A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die. | 07-26-2012 |
20120261817 | Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution - A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer. | 10-18-2012 |
20130075922 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SUBSTRATE EMBEDDED DUMMY-DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle. | 03-28-2013 |
20130113092 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 05-09-2013 |
20130127039 | Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface - A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking. | 05-23-2013 |
20130175696 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 07-11-2013 |
20140077381 | Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants - A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die. | 03-20-2014 |
20140110861 | Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support - A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer. | 04-24-2014 |
20140246779 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 09-04-2014 |
20150084213 | Semiconductor Device and Method of Controlling Warpage in Reconstituted Wafer - A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced. | 03-26-2015 |
Patent application number | Description | Published |
20100148347 | CHIP SCALE PACKAGE STRUCTURE WITH CAN ATTACHMENT - A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test. | 06-17-2010 |
20100148363 | STEP CAVITY FOR ENHANCED DROP TEST PERFORMANCE IN BALL GRID ARRAY PACKAGE - A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder balls may be set out by rows and columns. A plurality of wires electrically connect the semiconductor chip to the solder balls. A layer of encapsulating compound is deposited over the semiconductor chip. A step cavity of a selected depth and shape is formed in the layer of encapsulating compound at or near the edge or periphery of the layer of encapsulating compound. The step cavity is separated from the solder balls by the substrate layer but spans over a plurality of selected solder balls. | 06-17-2010 |
20110156230 | MULTI-STACKED SEMICONDUCTOR DICE SCALE PACKAGE STRUCTURE AND METHOD OF MANUFACTURING SAME - A multi-stack semiconductor dice assembly has enhanced board-level reliability and integrated electrical functionalities over a common package foot-print. The multi-stack semiconductor dice assembly includes a bottom die having a stepped upper surface. The stepped upper surface includes a base region and a stepped region, which is raised relative to the base region. The base region includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls. An upper die is stacked above the bottom die. The upper die includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls and are arranged to align with the attachment structures of the bottom die. Electrically conductive balls are attached to the attachment structures of the bottom die and the attachment structures of the upper die. | 06-30-2011 |
20110156240 | RELIABLE LARGE DIE FAN-OUT WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURE - A fan-out wafer level package includes a semiconductor die with contact pads positioned on a top surface. A fan-in redistribution layer positioned over the die includes contact pads in electrical communication with the first contact pads of the die. A buffer layer positioned over the fan-in layer includes a plurality of vias, in electrical contact with the contact pads of the fan-in layer. A fan-in redistribution layer is positioned over the buffer layer and includes contact pads on a surface opposite the buffer layer, in electrical communication with the vias. The semiconductor die, fan-in layer, and buffer layer are encapsulated in a molding com-pound layer. Solder contacts, for electrically connecting the semiconductor device to a electronic circuit board, are positioned on contact pads of the fan-out layer. The buffer layer has a substantial thickness, to reduce and distribute shear stresses resulting from thermal mismatch of coefficients of thermal expansion of the semiconductor die and a circuit board. | 06-30-2011 |
20110156250 | FLIP-CHIP FAN-OUT WAFER LEVEL PACKAGE FOR PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE - A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto. | 06-30-2011 |
20110157452 | FAN-OUT WAFER LEVEL PACKAGE FOR AN OPTICAL SENSOR AND METHOD OF MANUFACTURE THEREOF - An optical sensor package has a transparent substrate with a redistribution layer formed on a face thereof, which includes a window and a plurality of electrically conductive traces. A semiconductor substrate, including an optical sensor and a plurality of contact terminals on a face thereof, is positioned on the transparent substrate in a face-to-face arrangement, with the optical sensor directly opposite the window, and with each of the contact terminals electrically coupled to a respective one of the electrically conductive terminals. The transparent substrate has larger overall dimensions than the semiconductor substrate, so that one or more edges of the transparent substrate extend beyond the corresponding edges of the semiconductor substrate. A plurality of solder balls are positioned on the face of the transparent substrate, each in electrical contact with a respective one of the electrically conductive terminals. The solder balls and the semiconductor substrate are at least partially encapsulated in an encapsulating layer formed on the face of the transparent substrate, which has been planarized to expose upper portions of the solder balls, as contact pads of the optical sensor package. | 06-30-2011 |
20110157853 | FAN-OUT WAFER LEVEL PACKAGE WITH POLYMERIC LAYER FOR HIGH RELIABILITY - A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit. | 06-30-2011 |
20120028397 | ULTRA-THIN QUAD FLAT NO-LEAD (QFN) PACKAGE - An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages. | 02-02-2012 |
20120168929 | LOW COST THERMALLY ENHANCED HYBRID BGA AND METHOD OF MANUFACTURING THE SAME - A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board. | 07-05-2012 |
20120178213 | CHIP SCALE PACKAGE STRUCTURE WITH CAN ATTACHMENT - A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test. | 07-12-2012 |
20130093072 | LEADFRAME PAD DESIGN WITH ENHANCED ROBUSTNESS TO DIE CRACK FAILURE - A leadframe includes a die pad and a protective wall surrounding the die pad. A semiconductor die is situated on the die pad. Indentations are formed on the four inner corners of the protective wall adjacent the corners of the semiconductor die. | 04-18-2013 |
20130127041 | BALL GRID ARRAY TO PIN GRID ARRAY CONVERSION - Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package. | 05-23-2013 |
20130147024 | BALANCED LEADFRAME PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion. | 06-13-2013 |
20130147052 | OFFSET OF CONTACT OPENING FOR COPPER PILLARS IN FLIP CHIP PACKAGES - An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die. | 06-13-2013 |
20130161806 | WINDOW CLAMP TOP PLATE FOR INTEGRATED CIRCUIT PACKAGING - A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding. | 06-27-2013 |
20140091443 | SURFACE MOUNT PACKAGE FOR A SEMICONDUCTOR INTEGRATED DEVICE, RELATED ASSEMBLY AND MANUFACTURING PROCESS - A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package. | 04-03-2014 |
20140113410 | SYSTEM IN PACKAGE MANUFACTURING METHOD USING WAFER-TO-WAFER BONDING - Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer. | 04-24-2014 |
20140291782 | METHODS AND DEVICES FOR PACKAGING INTEGRATED CIRCUITS - Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package. | 10-02-2014 |
20140291812 | SEMICONDUCTOR PACKAGES HAVING AN ELECTRIC DEVICE WITH A RECESS - Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets. | 10-02-2014 |
20150084171 | NO-LEAD SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed. | 03-26-2015 |
Patent application number | Description | Published |
20110261887 | METHODS AND DEVICES FOR ESTIMATING MOTION IN A PLURALITY OF FRAMES - In various embodiments, a method for estimating motion in a plurality of frames is provided, the method including determining a first set of motion vectors with respect to a first frame and a second frame, the second frame being in succession with the first frame along a time direction, determining a second set of motion vectors with respect to a predicted frame and the second frame, the predicted frame being in succession with the first frame along the time direction; wherein some motion vectors of the second set of motion vectors are interpolated from motion vectors of the first set of motion vectors; and determining a third set of motion vectors based on the first set of motion vectors and the second set of motion vectors. | 10-27-2011 |
20120014451 | Image Encoding Methods, Image Decoding Methods, Image Encoding Apparatuses, and Image Decoding Apparatuses - In an embodiment, an image encoding method is provided. The image encoding method may include a first partial encoding step, wherein first partially encoded image data is generated based on first input data after the first input data is available; a second partial encoding step, wherein second partially encoded image data is generated based on second input data after the second input data is available, before the first input data is available; and an encoded image data generating step, wherein encoded image data is generated based on the first partially encoded image data and the second partially encoded image data. | 01-19-2012 |
20120063695 | METHODS FOR ENCODING A DIGITAL PICTURE, ENCODERS, AND COMPUTER PROGRAM PRODUCTS - In one embodiment, a method for encoding a digital picture of a sequence of digital pictures is provided, the digital picture comprising a plurality of pixels, wherein the plurality of pixels is associated at least partially with a first group of pixels and the plurality of pixels or a plurality of pixels of another digital picture is associated at least partially with at least one second group of pixels. The method comprises determining, for the second group of pixels, a second group of pixels coding mode, determining, for the first group of pixels, based on the second group of pixels coding mode, a first group of pixels coding mode, and encoding the digital picture using the first group of pixels coding mode for the first group of pixels. | 03-15-2012 |
20130004096 | Methods, Devices, and Computer Readable Mediums for Processing a Digital Picture - Embodiments provide a method for processing a digital picture, wherein the digital picture comprises a plurality of pixels. The method comprises dividing the digital picture into a plurality of blocks, each block comprising a plurality of pixels. The method further comprises determining a type of block for each block. The method further comprises associating each block with a filtering mode of a plurality of different filtering modes according to the type determined for the block. The method further comprises filtering each block using the associated filtering mode associated with the block. | 01-03-2013 |
20130287315 | METHOD, AN APPARATUS AND A COMPUTER PROGRAM PRODUCT FOR DEINTERLACING AN IMAGE HAVING A PLURALITY OF PIXELS - According to example embodiments, a method for deinterlacing an image having a plurality of pixels, the method comprising: calculating a difference between a first pixel of the image and each pixel of at least one pixel pair, each pixel pair comprising one pixel being positioned above the first pixel and another pixel being positioned below the first pixel; and deinterlacing the first pixel only if at least one difference corresponding to a pixel pair exceeds a predefined threshold. A corresponding apparatus and computer program product are also provided. | 10-31-2013 |
20130301741 | METHOD AND APPARATUS FOR PACKETIZING DATA - A method for packetizing data representing a video sequence comprising a first frame and a second frame. The method comprising determining for at least one first area of a plurality of first areas of the first frame a second area of a plurality of second areas of the second frame such that, for different first areas different second areas are determined and such that, for each of the first areas, a measure of the distance between the second area determined for the first area and an area of the second frame whose location within the second frame corresponds to the location of the first area is above a value. The method further comprising grouping, for each of the first areas, data which the first area may be reconstructed and data from which the second area determined for the first area may be reconstructed into a packet. | 11-14-2013 |
Patent application number | Description | Published |
20090204092 | BODY ADHERING ABSORBENT ARTICLE - In a body adhering absorbent article, an absorbent structure is configured for disposition adjacent a female wearer's vaginal region to absorb bodily fluids discharged by the wearer. A shell supports the absorbent structure at the vaginal region and has an adhesive on a body-facing surface thereof for adhering the shell directly to the wearer. A placement aid is disposed on at least one of the absorbent structure and the shell to facilitate placement on the wearer. Securement components may be provided for securing the article in a folded configuration during wear and/or to the wearer's undergarment. Detachment components may also be provided to facilitate detachment of the article from the wearer. | 08-13-2009 |
20100152692 | Article with fluid-activated barriers - An absorbent article has a longitudinal direction, a transverse direction, a first major surface which forms a body-facing surface of the absorbent article, and a second major surface disposed distally from the first major surface which forms a garment-facing surface of the absorbent article. The article includes an absorbent core positioned between the first major surface and the second major surface. The article also includes at least one barrier structure having an inward-facing side and an outward-facing side, and at least one liquid shrinkable string. The at least one barrier structure is disposed on the first major surface, and the inward-facing side of the at least one barrier structure is attached to the absorbent article. In addition, a first portion of the at least one liquid shrinkable string is attached to the at least one barrier structure. | 06-17-2010 |
20120215192 | REMOVAL OF COLORED SUBSTANCES FROM AQUEOUS LIQUIDS - The use of a decolorizing composition for removing colored substances from aqueous fluids (e.g., colored pigments, blood-containing fluids, etc.) is provided. The decolorizing composition contains one or more inorganic salts. In one embodiment, for example, the composition contains a mixture of sodium sulfate (Na | 08-23-2012 |
20130261584 | Absorbent Articles with Decolorizing Agents - A feminine hygiene absorbent personal care article includes a topsheet layer, a backsheet layer, at least one absorbent core layer positioned between the topsheet layer and the backsheet layer and decolorizing agents positioned on at least one decolorizing agent-containing layer, adjacent the article side edges, with the decolorizing agent-containing layer extending laterally beyond the lateral side edges of the absorbent core layer and being noncontinuous over at least a portion of the article in the article transverse direction. | 10-03-2013 |
20130261586 | Absorbent Articles with Improved Stain Decolorization - Disclosed herein is a personal care absorbent article such as a feminine hygiene absorbent personal care article for receiving a body exudate such as menses. The article includes a topsheet layer, a backsheet layer, at least one absorbent core layer positioned between the topsheet layer and the backsheet layer, optionally a pair of wings, and a decolorization means associated with the article for altering the visual appearance and/or physical characteristics of the a body exudate. The use of the decolorization means provides several benefits to the end user including the creation of a visually smaller stain on the top surface of the topsheet layer and a possible reduction in staining of the wearer's apparel should the body exudate leak from or off of the article being worn. | 10-03-2013 |
Patent application number | Description | Published |
20110148602 | METHOD AND A SYSTEM FOR DETERMINING THE LOCATION OF A SUBJECT, AND A RADIO FREQUENCY IDENTIFICATION TAG ASSEMBLY - According to one embodiment of the present invention, a method for determining the location of a subject is provided. The method includes receiving, by a first set of receivers out of a plurality of receivers, a first signal from a radio frequency identification tag being assigned to the subject, wherein the radio frequency identification tag has assigned a radio frequency identification tag identity; receiving, by a second set of receivers out of a plurality of receivers, a second signal from the radio frequency identification tag, the second signal being different from the first signal, wherein the second set of receivers is different from the first set of receivers; computing a location score based on an information about the first signal, wherein the information about the first signal is included in the first signal and on the first set of receivers, and further based on an information about the second signal, wherein the information about the second signal is included in the second signal and on the second set of receivers; and determining the location of the subject based on the location score. A system for determining the location of a subject is also provided. A radio frequency identification tag assembly is also provided. | 06-23-2011 |
20120316794 | METHOD AND A SYSTEM FOR MONITORING A PHYSIOLOGICAL PARAMETER OF A SUBJECT - Embodiments provide a method which includes transmitting, by a receiving device (RD), a request message which includes a receiving device identification number (RDIN); receiving, by the RD, a registration message including a measuring device identification number (MDIN) from a measuring device (MD); registering, by the RD, the MD by means of the MDIN if the registration message from the MD includes the RDIN; receiving, by the RD, one or more data messages from the MD, each data message including the MDIN and a physiological parameter; and processing the physiological parameter in each data message, by the RD, if the MD has been registered by the RD. The range of the transmission of the request message between the RD and the MD is shorter than the range of the transmission of each data message between the MD and the RD, and/or the range of the transmission of the registration message between the MD and the RD is shorter than the range of the transmission of each data message between the MD and the RD. Embodiments also provide a corresponding monitoring system. | 12-13-2012 |
20140070011 | METHOD AND A SYSTEM FOR DETERMINING THE LOCATION OF A SUBJECT, AND A RADIO FREQUENCY IDENTIFICATION TAG ASSEMBLY - According to one embodiment of the present invention, a method for determining the location of a subject is provided. The method includes receiving, by a first set of receivers out of a plurality of receivers, a first signal from a radio frequency identification tag being assigned to the subject, wherein the radio frequency identification tag has assigned a radio frequency identification tag identity; receiving, by a second set of receivers out of a plurality of receivers, a second signal from the radio frequency identification tag, the second signal being different from the first signal, wherein the second set of receivers is different from the first set of receivers; computing a location score based on an information about the first signal, wherein the information about the first signal is included in the first signal and on the first set of receivers, and further based on an information about the second signal, wherein the information about the second signal is included in the second signal and on the second set of receivers; and determining the location of the subject based on the location score. A system for determining the location of a subject is also provided. A radio frequency identification tag assembly is also provided. | 03-13-2014 |