Patent application number | Description | Published |
20110002087 | Stacked capacitor with positive multi-pin structure - A stacked capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit has a positive electrode that has a positive pin extended outwards therefrom. The positive pins of the capacitor units are divided into a plurality of positive pin units that are separated from each other, and the positive pins of each positive pin unit are electrically stacked onto each other. Each capacitor unit has a negative electrode, and the negative electrodes of the capacitor units are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins of the capacitor units and a negative guiding substrate electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit. | 01-06-2011 |
20110007451 | STACKED SOLID ELECTROLYTIC CAPACITOR WITH MULTI-PIN STRUCTURE - A stacked solid electrolytic capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. The positive electrode of each capacitor unit has a positive pin extended outwards therefrom. The positive pins are divided into a plurality of positive pin units that are separated from each other and electrically stacked onto each other. The negative electrode of each capacitor unit has a negative pin extended outwards therefrom. The negative pins are divided into a plurality of negative pin units. The negative pin units are separated from each other and the negative pins of each negative pin unit are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins and a negative guiding substrate electrically connected to the negative pins. The package unit covers the capacitor units and one part of the substrate unit. | 01-13-2011 |
20110007452 | Lamellar Stacked Solid Electrolytic Capacitor - A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit. | 01-13-2011 |
20110122544 | STACKED SOLID ELECTROLYTIC CAPACITOR AND A METHOD FOR MANUFACTURING THE SAME - A stacked solid electrolytic capacitor and a method for manufacturing the same are disclosed. The stacked solid electrolytic capacitor includes two capacitor sets, a positive electrode conducting device, a negative electrode conducting device, and a package unit. Each capacitor set includes at least one capacitor unit. The front side of the positive electrode portion of the capacitor set extends to form a positive electrode pin. The positive electrode conducting device has at least one first positive electrode conducting lead frame and at least one second positive electrode conducting lead frame. The first positive electrode conducting lead frame is electrically connected with the second positive electrode conducting lead frame. The negative electrode conducting device has at least one negative electrode conducting lead frame, and is electrically connected with the negative electrode of the two capacitor sets by using metal conductive material. | 05-26-2011 |
20110216475 | STACKED SOLID-STATE ELECTROLYTIC CAPACITOR WITH MULTI-DIRECTIONAL PRODUCT LEAD FRAME STRUCTURE - A stacked solid-state electrolytic capacitor with multi-directional product lead frame structure includes a plurality of capacitor units, a substrate unit and a package unit. The capacitor units are stacked onto each other. Each capacitor unit has a positive electrode and a negative electrode, the positive electrode of each capacitor unit has a positive pin extended outwards, the positive pins are electrically stacked onto each other, and the negative electrodes are electrically stacked onto each other. The substrate unit has at least one positive guiding substrate electrically connected to the positive pins of the capacitor units and a plurality of negative guiding substrates electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit in order to expose an end of the at least one positive guiding substrate and an end of each negative guiding substrate. | 09-08-2011 |
20120099247 | SOLID ELECTROLYTIC CAPACITOR HAVING A PROTECTIVE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A solid electrolytic capacitor with a protective structure, which includes stacked capacitor elements electrically connected to the positive and negative terminal. A packaging material such as synthetic resin is used to encapsulate the capacitor elements, the positive terminal, and the negative terminal. Before packaging, a protective layer is formed by a colloid material, which covers the main body of the capacitor that includes the capacitor elements, the positive terminal, and the negative terminal. The protective layer provides a better seal and relieves the external pressure exerting on the capacitor during the packaging process. The protection prevents structural damage to the capacitor's main body while reducing the risk of short-circuits and excessive current leakage. | 04-26-2012 |
20130010404 | CAPACITANCE UNIT AND STACKED SOLID ELECTROLYTIC CAPACITOR - A capacitance unit includes an anode portion, an insulating portion, a cathode portion and a colloid portion. The front end of the anode portion extends to from an anode terminal. The insulating portion surrounds the anode portion and covers a first partial surface of the anode portion. The cathode portion is disposed next to the insulating portion, and the cathode portion covers a second partial surface of the anode portion. The colloid portion is disposed next to the insulating portion, and the colloid portion surrounds the cathode portion and covers a partial surface of the cathode portion. | 01-10-2013 |
20130258555 | CAPACITOR UNIT AND STACKED SOLID ELECTROLYTIC CAPACITOR HAVING THE SAME - The present invention relates to a capacitor unit, which includes an anode portion, a cathode portion, and an insulating portion. The insulating portion is provided for in a form of a headband to partially cover the surface of the anode portion to divide the anode and the cathode portions. The cathode portion partially covers the anode portion and is located behind the insulating portion. The cathode portion has at least one conductive layer which is made of a conductive polymer having copper, copper alloy, or a mixture thereof. | 10-03-2013 |
20140071589 | WINDING-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE - A winding-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The conductive unit includes a winding-type capacitor having a first conductive pin and a second conductive pin. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal electrically connected to the first conductive pin and a second conductive terminal electrically connected to the second conductive pin. The first conductive terminal has a first embedded portion contacting the first conductive pin and enclosed by the package body and a first exposed portion connected to the first embedded portion and exposed from the package body. The second conductive terminal has a second embedded portion contacting the second conductive pin and enclosed by the package body and a second exposed portion connected to the second embedded portion and exposed from the package body. | 03-13-2014 |
20140071590 | STACKED-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE - A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The capacitor unit includes a plurality of capacitors stacked on top of one another. The package unit includes a package body enclosing the capacitors. The package body has a top surface defining a package length, a package width and an effective package, and the package width is substantially between 85% and 95% of the package length. The conductive unit includes a first conductive terminal electrically connected to the positive portion of the capacitor and a second conductive terminal electrically connected to the negative portion of the capacitor. One part of the first conductive terminal and one part of the second conductive terminal are enclosed by the package body, and another part of the first conductive terminal and another part of the second conductive terminal are exposed from the package body. | 03-13-2014 |
20140078647 | STACKED-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE HAVING A PLURALITY OF NEGATIVE LEAD PINS AND METHOD OF MANUFACTURING THE SAME - A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The conductive unit includes a plurality of stacked-type capacitors stacked on top of one another and electrically connected with each other, and each stacked-type capacitor has a positive portion and a negative portion. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal and a second conductive terminal. The first conductive terminal has a first embedded portion electrically connected to the positive portion and enclosed by the package body and a first lateral exposed portion connected to the first embedded portion. The second conductive terminal has a second lateral exposed portion, a second front exposed portion, a second rear exposed portion, and a second embedded portion electrically connected to the negative portion and enclosed by the package body. | 03-20-2014 |
20140307365 | SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE FOR DECREASING EQUIVALENT SERIES RESISTANCE AND METHOD OF MANUFACTURING THE SAME - A solid electrolytic capacitor package structure for decreasing equivalent series resistance (ESR), includes a capacitor unit, a package unit and a conductive unit. The capacitor unit includes a plurality of first stacked-type capacitors sequentially stacked on top of one another and electrically connected with each other. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal and a second conductive terminal having a through hole, and the stacked-type capacitors are electrically connected between the first and the second conductive terminals. The bottommost first stacked-type capacitor is positioned on the top surface of the second conductive terminal through conductive paste that has a first conductive portion disposed between the bottommost first stacked-type capacitors and the top surface of the second conductive terminal and a second conductive portion filling in the through groove to connect with the first conductive portion. | 10-16-2014 |
20150121672 | METHOD OF MANUFACTURING A STACKED-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE HAVING A PLURALITY OF NEGATIVE LEAD PINS - A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The conductive unit includes a plurality of stacked-type capacitors stacked on top of one another and electrically connected with each other, and each stacked-type capacitor has a positive portion and a negative portion. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal and a second conductive terminal. The first conductive terminal has a first embedded portion electrically connected to the positive portion and enclosed by the package body and a first lateral exposed portion connected to the first embedded portion. The second conductive terminal has a second lateral exposed portion, a second front exposed portion, a second rear exposed portion, and a second embedded portion electrically connected to the negative portion and enclosed by the package body. | 05-07-2015 |
20150194262 | SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME, AND CONDUCTIVE UNIT - A solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes at least one first conductive terminal and at least one second conductive terminal. The first conductive terminal includes a first core layer and a first enclosing layer. The first core layer has a first top exposed surface exposed from the first enclosing layer, and the first top exposed surface has a first top covering area covered by the package body. The second conductive terminal includes a second core layer and a second enclosing layer. The second core layer has a second top exposed surface exposed from the second enclosing layer, and the second top exposed surface has a second top covering area covered by the package body. | 07-09-2015 |
Patent application number | Description | Published |
20140035664 | VOLTAGE PROVIDING CIRCUIT - A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage. | 02-06-2014 |
20140036608 | TRACKING SIGNALS IN MEMORY WRITE OR READ OPERATION - A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal. | 02-06-2014 |
20140084374 | CELL DESIGN - One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down transistor, respectively associated one or more gate to gate distances. In some embodiments, a second gate to gate distance is selected based on a first gate to gate distance. For example, the first gate to gate distance and the second gate to gate distance are associated with a first transistor. In another example, the first gate to gate distance is associated with a first transistor and the second gate to gate distance is associated with a second transistor. In this manner, a cell design is provided to improve a static noise margin (SNM) or a write margin (WM) for the cell, for example. | 03-27-2014 |
20140269110 | ASYMMETRIC SENSING AMPLIFIER, MEMORY DEVICE AND DESIGNING METHOD - A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current. | 09-18-2014 |
20140269114 | CIRCUIT FOR MEMORY WRITE DATA OPERATION - A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage. The voltage adjustment circuitry has a plurality of selectable transistors that when individually selected have a cumulative effect to pull the reduced supply voltage down further. The timing adjustment circuitry has a plurality of selectable multiplexers that when individually selected for a delayed voltage transition have a cumulative effect to delay return of voltage supplied to SRAM from a reduced supply voltage to a nominal supply voltage. | 09-18-2014 |
20150092502 | CIRCUIT TO GENERATE A SENSE AMPLIFIER ENABLE SIGNAL - A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal. The detection unit is coupled to the tracking bit line and configured to generate a sense amplifier enable (SAE) signal in response to the voltage level on the tracking bit line. | 04-02-2015 |
20150102853 | WAKE UP BIAS CIRCUIT AND METHOD OF USING THE SAME - A wake up circuit includes a bias signal control block configured to receive a sleep signal and to generate a plurality of bias control signals. The wake up circuit further includes a bias supply block configured to receive each bias control signal of the plurality of bias control signals and to generate a header bias signal. The bias supply block includes a first bias stage configured to receive a first bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a first voltage. The bias supply block further includes a second bias stage configured to receive a second bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a second voltage different from the first voltage. The wake up circuit further includes a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal. | 04-16-2015 |
20150138902 | THREE-DIMENSIONAL (3-D) WRITE ASSIST SCHEME FOR MEMORY CELLS - An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells. | 05-21-2015 |
Patent application number | Description | Published |
20110266674 | Laser Etch Via Formation - The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed. | 11-03-2011 |
20120012871 | LIGHT EMITTING DEVICE - The present disclosure relates to methods for performing wafer-level measurement and wafer-level binning of LED devices. The present disclosure also relates to methods for reducing thermal resistance of LED devices. The methods include growing epitaxial layers consisting of an n-doped layer, an active layer, and a p-doped layer on a wafer of a growth substrate. The method further includes forming p-contact and n-contact to the p-doped layer and the n-doped layer, respectively. The method further includes performing a wafer-level measurement of the LED by supplying power to the LED through the n-contact and the p-contact. The method further includes dicing the wafer to generate diced LED dies, bonding the diced LED dies to a chip substrate, and removing the growth substrate from the diced LED dies. | 01-19-2012 |
20120032212 | METHOD OF LIGHT EMITTING DIODE SIDEWALL PASSIVATION - A Light-Emitting Diode (LED) includes a light-emitting structure having a passivation layer disposed on vertical sidewalls across a first doped layer, an active layer, and a second doped layer that completely covers at least the sidewalls of the active layer. The passivation layer is formed by plasma bombardment or ion implantation of the light-emitting structure. It protects the sidewalls during subsequent processing steps and prevents current leakage around the active layer. | 02-09-2012 |
20120064642 | METHOD TO REMOVE SAPPHIRE SUBSTRATE - A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching. | 03-15-2012 |
20120080698 | HIGH EFFICIENCY LIGHT EMITTING DIODES - The present disclosure relates to high efficiency light emitting diode devices and methods for fabricating the same. In accordance with one or more embodiments, a light emitting diode device includes a substrate having one or more recessed features formed on a surface thereof and one or more omni-directional reflectors formed to overlie the one or more recessed features. A light emitting diode layer is formed on the surface of the substrate to overlie the omni-directional reflector. The one or more omni-directional reflectors are adapted to efficiently reflect light. | 04-05-2012 |
20120104409 | FORMING LIGHT-EMITTING DIODES USING SEED PARTICLES - A seed layer for growing a group III-V semiconductor structure is embedded in a dielectric material on a carrier substrate. After the group III-V semiconductor structure is grown, the dielectric material is removed by wet etch to detach the carrier substrate. The group III-V semiconductor structure includes a thick gallium nitride layer of at least 100 microns or a light-emitting structure. | 05-03-2012 |
20120126262 | ETCHING GROWTH LAYERS OF LIGHT EMITTING DEVICES TO REDUCE LEAKAGE CURRENT - The present disclosure relates to methods for fabricating LEDs by patterning and etching an n-doped epitaxial layer to form regions of roughened surface of the n-doped layer and mesa structures adjacent to the roughened surface regions before depositing an active layer and the rest of the epitaxial layers on the mesa structures. The method includes growing epitaxial layers of an LED including an un-doped layer and an n-doped layer on a wafer of growth substrate. The method also includes patterning the n-doped layer to form a first region of the n-doped layer and a mesa region of the n-doped layer adjacent to the first region. The method further includes etching the first region of the n-doped layer to create a roughened surface. The method further includes growing additional epitaxial layers of the LED including an active layer and a p-doped layer on the mesa region of the n-doped layer. | 05-24-2012 |
20120205694 | METHOD OF FORMING A LIGHT EMITTING DIODE EMITTER SUBSTRATE WITH HIGHLY REFLECTIVE METAL BONDING - The present disclosure provides one embodiment of a method for fabricating a light emitting diode (LED) package. The method includes forming a plurality of through silicon vias (TSVs) on a silicon substrate; depositing a dielectric layer over a first side and a second side of the silicon substrate and over sidewall surfaces of the TSVs; forming a metal layer patterned over the dielectric layer on the first side and the second side of the silicon substrate and further filling the TSVs; and forming a plurality of highly reflective bonding pads over the metal layer on the second side of the silicon substrate for LED bonding and wire bonding. | 08-16-2012 |
20120228650 | Light Emitting Diode Emitter Substrate with Highly Reflective Metal Bonding - The present disclosure provides one embodiment of a method for fabricating a light emitting diode (LED) package. The method includes forming a plurality of through silicon vias (TSVs) on a silicon substrate; depositing a dielectric layer over a first side and a second side of the silicon substrate and over sidewall surfaces of the TSVs; forming a metal layer patterned over the dielectric layer on the first side and the second side of the silicon substrate and further filling the TSVs; and forming a plurality of highly reflective bonding pads over the metal layer on the second side of the silicon substrate for LED bonding and wire bonding. | 09-13-2012 |
20120273749 | METHOD AND STRUCTURE FOR LED WITH NANO-PATTERNED SUBSTRATE - The present disclosure provides one embodiment of a method for fabricating light-emitting diode (LED) devices. The method includes forming a nano-mask layer on a first substrate, wherein the nano-mask layer has a randomly arranged grain pattern; growing a first epitaxy semiconductor layer in the first substrate, forming a nano-composite layer; growing a number of epitaxy semiconductor layers over the nano-composite layer; bonding a second substrate to the epitaxy semiconductor layers from a first side of the epitaxy semiconductor layers; applying a radiation energy to the nano-composite layer; and separating the first substrate from the epitaxy semiconductor layers from a second side of the epitaxy semiconductor layers. | 11-01-2012 |
20130095581 | THICK WINDOW LAYER LED MANUFACTURE - A LED die and method for bonding, dicing, and forming the LED die are disclosed. In an example, the method includes forming a LED wafer, wherein the LED wafer includes a substrate and a plurality of epitaxial layers disposed over the substrate, wherein the plurality of epitaxial layers are configured to form a LED; bonding the LED wafer to a base-board to form a LED pair; and after bonding, dicing the LED pair, wherein the dicing includes simultaneously dicing the LED wafer and the base-board, thereby forming LED dies. | 04-18-2013 |
20130140592 | LIGHT EMITTING DIODE WITH IMPROVED LIGHT EXTRACTION EFFICIENCY AND METHODS OF MANUFACTURING SAME - A light emitting diode structure and methods of manufacturing the same are disclosed. In an example, a light emitting diode structure includes a crystalline substrate having a thickness that is greater than or equal to about 250 μm, wherein the crystalline substrate has a first roughened surface and a second roughened surface, the second roughened surface being opposite the first roughened surface; a plurality of epitaxy layers disposed over the first roughened surface, the plurality of epitaxy layers being configured as a light emitting diode; and another substrate bonded to the crystalline substrate such that the plurality of epitaxy layers are disposed between the another substrate and the first roughened surface of the crystalline substrate. | 06-06-2013 |
20130187122 | PHOTONIC DEVICE HAVING EMBEDDED NANO-SCALE STRUCTURES - The present disclosure involves a method of fabricating a lighting apparatus. The method includes forming a first III-V group compound layer over a substrate. The first III-V group compound layer has a first type of conductivity. A multiple quantum well (MQW) layer is formed over the first III-V group compound layer. A second III-V group compound layer is then formed over the MQW layer. The second III-V group compound layer has a second type of conductivity different from the first type of conductivity. Thereafter, a plurality of conductive components is formed over the second III-V group compound layer. A light-reflective layer is then formed over the second III-V group compound layer and over the conductive components. The conductive components each have better adhesive and electrical conduction properties than the light-reflective layer. | 07-25-2013 |
20130260484 | OPTIMIZING LIGHT EXTRACTION EFFICIENCY FOR AN LED WAFER - The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters. | 10-03-2013 |
20140021483 | Forming Light-Emitting Diodes Using Seed Particles - A seed layer for growing a group | 01-23-2014 |
20150108424 | Method to Remove Sapphire Substrate - A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching. | 04-23-2015 |
Patent application number | Description | Published |
20090203346 | DOWN-CONVERTER AND CALIBRATION METHOD THEREOF - A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor. | 08-13-2009 |
20090213764 | FULL DIVISION DUPLEX SYSTEM AND A LEAKAGE CANCELLATION METHOD - An exemplary embodiment of a full division duplex system comprises a receiver, a transmitter and an auxiliary circuit. The receiver receives an inbound RF signal of a first band to generate an inbound baseband signal, and the transmitter up converts an outbound baseband signal by an oscillation signal to generate an outbound RF signal of a second band for transmission. The auxiliary circuit calculates leakages from the outbound RF signal to generate a blocker replica, in which a LNA is coupled to a non-conductive coupling path extended from the input of receiver to collect leakages from the outbound RF signal to produce an induction signal. The induction signal is down converted to perform an adjustment, and thereafter up converted again to generate the blocker replica. In this way, the inbound baseband signal is generated from a subtraction of the inbound RF signal and the blocker replica. | 08-27-2009 |
20090305656 | DIRECT CONVERSION RECEIVER AND DC OFFSET CONCELLATION METHOD - A direct conversion receiver and a DC offset cancellation method are provided. An RF module receives a transmission signal to generate an RF signal. A mixer converts the RF signal to a mixer output comprising baseband and imaginary parts. A filter module filters out the imaginary part of the mixer output and adjusts gain of the baseband part to generate a baseband signal. A calibrator performs a calibration to determine a mismatch value of the mixer. A static DC offset canceller provides a constant offset compensation according to the mismatch value; wherein the mismatch value is used to minimize component mismatching effects of the mixer. | 12-10-2009 |
20100317303 | SELF-CALIBRATING DIRECT CONVERSION TRANSMITTER WITH CONVERTING/STEERING DEVICE - A steering and mixing module comprises a double balanced switch quad and a steering quad. The double balanced switch quad comprises a first output pair, and the first output pair is coupled to a first load stage. The steering quad comprises a second output pair, and the second output pair is coupled to a second load stage. The double balanced switch quad and the steering quad share an input pair. | 12-16-2010 |
Patent application number | Description | Published |
20100172517 | Microphone Preamplifier Circuit and Voice Sensing Devices - A microphone preamplifier circuit is provided. An amplifier comprises a first input end, a second input end, and an output end. A bias voltage is provided by a bias voltage source. A first sensor is coupled to the first input end and the bias voltage source for sensing a first physical parameter and a second physical parameter. A second sensor is coupled to the second input end and the bias voltage source for sensing the first physical parameter, wherein the second sensor is insensitive to the second physical parameter. The output end of the amplifier outputs a difference of the first and second input ends whereby noises and interferences are reduced. | 07-08-2010 |
20100177913 | MICROPHONE PREAMPLIFIER CIRCUIT AND VOICE SENSING DEVICES - A microphone preamplifier circuit is provided in a system on chip. An amplifier comprises a first input end, a second input end, and an output end. A bias voltage is provided by a bias voltage source. A first sensor is coupled to the first input end and the bias voltage source for sensing a first physical parameter and a second physical parameter. A second sensor is coupled to the second input end and the bias voltage source for sensing the first physical parameter, wherein the second sensor is insensitive to the second physical parameter. The output end of the amplifier outputs a difference of the first and second input ends whereby noises and interferences are reduced. | 07-15-2010 |
20100322440 | AUDIO PROCESSING CIRCUIT AND PREAMPLIFIER CIRCUIT - An audio processing circuit is provided, receiving a microphone signal from a microphone to output a differential signal. A preamplifier receives the microphone signal to output a first preamplified voltage and a second preamplified voltage. A gain stage receives the first preamplified voltage and the second preamplified voltage to output the differential signal comprising a first differential output and a second differential output. In the preamplifier, a first operational amplifier is provided. A first voltage controlled current source is controlled by the output end of the first operational amplifier to provide a first current. A first transistor has a gate coupled to a ground voltage supply, a source coupled to the first voltage controlled current source for receiving the first current, and a drain coupled to a voltage ground. Likewise, a second voltage controlled current source and a second transistor are presented symmetrically to render the differential output. | 12-23-2010 |
20120128180 | Analog-to-Digital Converter and Analog-to-Digital Conversion Method - The invention provides an analog-to-digital converter. In one embodiment, the analog-to-digital converter receives a first audio signal from a microphone, and comprises a coding selection module, a pre-amplifier, a | 05-24-2012 |
20120128181 | Analog-to-Digital Converter, Sound Processing Device, and Method for Analog-to-Digital Conversion - The invention provides a sound processing device. In one embodiment, the sound processing device comprises a first microphone, a first analog-to-digital converter, a second microphone, and a second analog-to-digital converter. The first microphone detects a first sound pressure to generate a first analog audio signal. The first analog-to-digital converter converts the first analog audio signal to a first digital audio signal. The second microphone detects a second sound pressure to generate a second analog audio signal. The second analog-to-digital converter converts the second analog audio signal to a second digital audio signal, encodes a third digital audio signal according to the second digital audio signal, receives the first digital audio signal and a clock signal, outputs data bits of the third digital audio signal when the clock signal oscillates to a logic low level, and outputs data bits of the first digital audio signal when the clock signal oscillates to a logic high level. | 05-24-2012 |
20120128182 | Analog-to-Digital Converter and Analog-to-Digital Conversion Method - The invention provides an analog-to-digital converter. In one embodiment, the analog-to-digital converter receives a first audio signal from a microphone sensor, and receives a first channel selection signal and a clock signal, and comprises a toggle detection module, a first data processing module, a second data processing module, and a multiplexer. The toggle detection module detects whether the first channel selection signal is toggling between a logic low level and a logic high level to generate a control signal. The first data processing module processes the first channel selection signal to generate a second channel selection signal. The second data processing module converts the first audio signal from analog to digital to generate a second audio signal. If the control signal indicates that the first channel selection signal is toggling between the logic low level and the logic high level, the multiplexer outputs data bits of the second channel selection signal as an output signal of the analog-to-digital converter when the clock signal oscillates to the logic high level, and outputs data bits of the second audio signal as the output signal of the analog-to-digital converter when the clock signal oscillates to the logic low level. | 05-24-2012 |
20120130517 | Analog-to-Digital Converter, Sound Processing Device, and Analog-to-Digital Conversion Method - The invention provides a sound processing device. In one embodiment, the sound processing device comprises a first microphone, a first analog-to-digital converter, a second microphone, and a second analog-to-digital converter. The first microphone detects a first sound pressure to generate a first analog audio signal. The first analog-to-digital converter converts the first analog audio signal from analog to digital to obtain a first digital audio signal. The second microphone detects a second sound pressure to generate a second analog audio signal. The second analog-to-digital converter receives the first digital audio signal and a clock signal, inverts the phase of the first digital audio signal to generate a third digital audio signal, converts the second analog audio signal from analog to digital to obtain a second digital audio signal, encodes a fourth digital audio signal according to the second digital audio signal, outputs data bits of the third digital audio signal when the clock signal oscillates to a logic low level, and outputs data bits of the fourth digital audio signal when the clock signal oscillates to a logic high level. | 05-24-2012 |
Patent application number | Description | Published |
20080277662 | SEMICONDUCTOR STRUCTURES - A semiconductor structure is disclosed. The semiconductor structure includes a polycrystal substrate, a first single crystal layer formed thereon and a second single crystal layer formed on the first single crystal layer. A variation of coefficients of thermal expansion (CTE) between the first single crystal layer and the polycrystal substrate is less than 25%. There is no lattice mismatch between the first single crystal layer and the polycrystal substrate. | 11-13-2008 |
20090152113 | Gas detection system - A gas detection system used for detecting a concentration of a gas in a second environment based on a concentration of the gas in a first environment is provided. The gas detection system may include a gas detecting device having two detection module, a first dielectric layer a second dielectric layer and a programmed control module. The control module may detect the voltage outputted by the first detection module to obtain the concentration of the gas in the second environment, when the detected voltage is smaller than a predetermined value. The control module may output a voltage signal to the second detection module and may detect the steady state current corresponding to the voltage signal to obtain the concentration of the gas in the second environment corresponding to the steady state current. | 06-18-2009 |
20100148133 | P-TYPE METAL OXIDE SEMICONDUCTOR MATERIAL AND FABRICATION METHOD THEREOF - A fabrication method for a p-type metal oxide semiconductor material is disclosed, including providing a lithium salt and a zinc salt to be mixed in a solution, wherein the solution is added a chelating agent to form a metal complex compound comprising lithium and zinc. A heating process for the metal complex compound to form a p-type metal oxide semiconductor material powder is performed, having a formula Li | 06-17-2010 |
20100163429 | GAS SENSING MATERIAL AND GAS SENSOR EMPLOYING THE SAME - Gas sensing material and gas sensor employing the same are provided. The gas sensing material includes an inorganic metal oxide and an organic polymer, wherein the organic polymer includes a repeat unit having the structure of | 07-01-2010 |
20100288348 | SOLAR CELL DEVICE AND METHOD FOR FABRICATING THE SAME - A solar cell device is provided, including a transparent substrate, a composite transparent conductive layer disposed over the transparent substrate, a photovoltaic element formed over the composite transparent conductive layer, and an electrode layer disposed over the photovoltaic element. In one embodiment, the composite transparent conductive layer includes a first transparent conductive layer and a second transparent conductive layer sequentially stacked over the transparent substrate, and the first transparent conductive layer is made of lithium and fluorine-codoped tin oxide and the second transparent conductive layer is made of a material selected from a group consisting of zinc oxide and titanium dioxide. | 11-18-2010 |
20120107631 | BONDING MATERIAL, METHOD, AND STRUCTURE - Disclosed is a bonding structure, including a heat dissipation substrate, a eutectic layer on the heat dissipation substrate, and a copper layer on the eutectic layer. The thermal dissipation substrate includes aluminum oxide, aluminum nitride, or zirconium oxide. The eutectic layer includes aluminum oxide, aluminum nitride, or zirconium oxide doped with zinc, tin, indium, or combinations thereof. | 05-03-2012 |
20140091302 | P-TYPE METAL OXIDE SEMICONDUCTOR MATERIAL THING - The disclosure provides a p-type metal oxide semiconductor material. The p-type metal oxide semiconductor material has the following formula: In | 04-03-2014 |
Patent application number | Description | Published |
20090098307 | MANUFACTURING METHOD FOR FAR-INFRARED IRRADIATING SUBSTRATE - A manufacturing method for a far-infrared irradiating substrate is provided. The manufacturing method comprises steps of providing a substrate, providing a far-infrared irradiating material and evaporating the far-infrared irradiating material to form a thin film onto the substrate. The far-infrared irradiating substrate provided by the present invention not only has a high emission coefficient of far-infrared ray, but also do not cause a potential exposure of an ionizing radiation. | 04-16-2009 |
20090246514 | ANTIREFLECTION STRUCTURE AND MANUFACTURING METHOD THEREOF - An antireflection structure is provided. The antireflection structure includes a substrate layer having a substrate refractive index; a first inorganic layer disposed on the substrate layer and having a first refractive index different from the substrate refractive index, where a thickness of the first inorganic layer is in a range of 1 to 40 nm; and a second inorganic layer disposed on the first inorganic layer and having a second refractive index different from the first refractive index. | 10-01-2009 |
20090246553 | REFLECTIVE FILM AND METHOD FOR MANUFACTURING THE SAME - A reflective film is provided. The reflective film includes a substrate; a middle layer disposed on the substrate and mainly having a crystallized transition metal; and a metal layer disposed on the middle layer. | 10-01-2009 |
20130256262 | In Situ Manufacturing Process Monitoring System of Extreme Smooth Thin Film and Method Thereof - An in situ manufacturing process monitoring system of extreme smooth thin film and method thereof, comprising a coating device for coating a thin film on at least one substrate during a coating process, an ion figuring device for processing a surface polishing process on the thin film, a control device electrically coupled to the coating device and the ion figuring device respectively for controlling the coating device and the ion figuring device processing the coating process and surface polishing process by adjusting at least one device parameter of the coating device and the ion figuring device, and an in situ monitoring device electrically coupled to the control device for in situ monitoring at least one optical parameter of the thin film. | 10-03-2013 |
Patent application number | Description | Published |
20100128802 | VIDEO PROCESSING CIUCUIT AND RELATED METHOD FOR MERGING VIDEO OUTPUT STREAMS WITH GRAPHICAL STREAM FOR TRANSMISSION - A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit coupled to the video generating unit and the graphic generating unit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream. | 05-27-2010 |
20120256957 | IMAGE PROCESSING METHOD OF PERFORMING SCALING OPERATIONS UPON RESPECTIVE DATA PORTIONS FOR MULTI-CHANNEL TRANSMISSION AND IMAGE PROCESSING APPARATUS THEREOF - An image processing method includes: deriving a plurality of first data portions from an original data of a first input image, wherein the first data portions correspond to a plurality of partial image areas within the first input image respectively; performing a plurality of scaling operations upon the first data portions respectively, and accordingly generating a plurality of first processed data portions; and outputting a plurality of display data portions through a plurality of channels respectively, wherein the display data portions are derived from at least the first processed data portions respectively. | 10-11-2012 |
20130265489 | VIDEO PROCESSING CIRCUIT AND RELATED METHOD FOR MERGING VIDEO OUTPUT STREAMS WITH GRAPHICAL STREAM FOR TRANSMISSION - A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream. | 10-10-2013 |
Patent application number | Description | Published |
20090284312 | TEST CIRCUIT FOR PROGRAMMABLE GAIN AMPLIFIER - A test circuit, for checking whether at least one programmable gain amplifier (PGA) operates correctly, includes a signal generator, a gain controller, a test level output circuit, a comparison circuit and an identifying circuit. The signal generator is utilized for outputting a test input signal to a PGA to generate a test output signal. The gain controller is utilized for outputting a gain control signal to the PGA to adjust a gain of the PGA. The test level output circuit is utilized for referring to the test output signal to output a first test level and a second test level. The comparison circuit is utilized for comparing the first and second test levels to generate a result signal. The identifying circuit is utilized for identifying whether the PGA operates correctly according to the result signal. | 11-19-2009 |
20100266144 | AUDIO PROCESSING CHIP AND AUDIO SIGNAL PROCESSING METHOD THEREOF - An audio processing chip includes a connecting port, an audio amplifier module and a pulse width modulation (PWM) control circuit. The connecting port receives a pulse width modulation (PWM) signal; the audio amplifier module amplifies an audio signal according to a control signal to thereby output an audio output signal; and the pulse width modulation (PWM) control circuit is coupled between the connecting port and the audio amplifier module, and outputs the control signal to the audio amplifier module according to the PWM signal to thereby control an operation of the audio amplifier module. | 10-21-2010 |
20140328381 | Electronic device, communication method, audio device and amplifier device using pulse density modulation for communication - The present invention discloses an electronic device using pulse density modulation for communication, comprising: a pulse density modulation interface; a first circuit to output a clock signal and a data signal through the pulse density modulation interface; and a second circuit to receive the clock and data signals and thereby determine whether the level change times of the data signal reach a predetermined threshold while the clock signal remains unchanged, so as to verify whether the clock and data signals satisfy a start protocol. In an embodiment of the present invention, the above-mentioned predetermined threshold is equal to or more than three. | 11-06-2014 |
20150049882 | AUDIO DEVICE AND AUDIO UTILIZATION METHOD HAVING HAPTIC COMPENSATION FUNCTION - The present invention discloses an audio device having haptic compensation function capable of compensating a haptic effect according to a power measuring result and an audio signal. An embodiment of the audio device comprises: an audio signal generating circuit operable to generate an audio signal; a power measuring circuit operable to measure a remaining electric quantity of a power source and thereby generate a power measuring result; and a haptic compensating circuit, coupled to the audio signal generating circuit and the power measuring circuit, operable to adjust a gain of the audio signal or the derived signal thereof according to the power measuring result and thereby output a haptic compensation signal which is used to compensate the haptic effect. | 02-19-2015 |
20150139437 | SIGNAL PROCESSING CIRCUIT AND ASSOCIATED SIGNAL PROCESSING METHOD APPLIED TO HEADSET - The present invention provides a signal processing circuit and a signal processing method applied to a headset. In the present invention, the signal processing circuit adjusts gain and phase of a left channel signal and a right channel signal to generate a first adjust signal, and a recorded sound from a microphone is added by the first adjust signal to cancel a coupled signal. In addition, the signal processing circuit adjusts gain and phase of the right channel signal to generate a second adjust signal, and the right channel signal is added by the second adjust signal to cancel a coupled signal; and the signal processing circuit adjusts gain and phase of the left channel signal to generate a third adjust signal, and the left channel signal is added by the third adjust signal to cancel a coupled signal. | 05-21-2015 |
Patent application number | Description | Published |
20120208129 | PROCESS FOR FORMING AN ANTI-OXIDANT METAL LAYER ON AN ELECTRONIC DEVICE - A process for forming an anti-oxidant metal layer on an electronic device comprises the steps of providing a substrate; forming a conductive metal layer on the substrate; forming a first photoresist layer on the conductive metal layer; patterning the first photoresist layer to form apertures and first grooves; forming a connecting member having a top surface and a lateral surface in the aperture and the first groove; removing the first photoresist layer to reveal the top surface and the lateral surface; forming a second photoresist layer on the conductive metal layer; patterning the second photoresist layer to form apertures and second grooves; forming an anti-oxidant metal layer in aperture and second groove, the anti-oxidant metal layer covers the top surface and the lateral surface of the connecting member; and removing the second photoresist layer to reveal the anti-oxidant metal layer and the conductive metal layer. | 08-16-2012 |
20120211257 | PYRAMID BUMP STRUCTURE - A pyramid bump structure for electrically coupling to a bond pad on a carrier comprises a conductive block disposed at the bond pad and an oblique pyramid insulation layer covered at one side of the conductive block. The oblique pyramid insulation layer comprises a bottom portion and a top portion, and outer diameter of the oblique pyramid insulation layer is tapered from the bottom portion to the top portion. When the carrier is connected with a substrate and an anisotropic conductive film disposed at the substrate, the pyramid bump structure may rapidly embed into the anisotropic conductive film to raise the flow rate of the anisotropic conductive film. Further, a short phenomenon between adjacent bumps can be avoided to raise the yield rate of package process. | 08-23-2012 |
20130181346 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer. | 07-18-2013 |
20130183823 | BUMPING PROCESS - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer. | 07-18-2013 |
20130193570 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer. | 08-01-2013 |
20130196498 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer. | 08-01-2013 |
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20100110950 | METHOD AND APPARATUS FOR ALIGNING POWER SAVINGS CLASSES - A method for power savings in a wireless communications network, including selecting all Type-1 power savings classes (PSCs), selecting all Type-2 PSCs, and selecting all Type-3 PSCs. The method further includes aligning the Type-1 PSCs of the device, if more than one Type-1 PSC is selected, and aligning the Type-2 PSCs of the device, if more than one Type-2 PSC is selected. The method also includes aligning the two or more aligned Type-1 PSCs or, if only one Type-1 PSC is selected, the Type-1 PSC, and the two or more aligned Type-2 PSCs or, if only one Type-2 PSC is selected, the Type-2 PSC, if there is at least one Type-1 PSC and at least one Type-2 PSC. The method may further include aligning the Type-3 PSCs with the aligned Type-1 and Type-2 PSCs, if there is at least one Type-3 PSC and at least one Type-1 or Type-2 PSC. | 05-06-2010 |
20100235666 | METHOD FOR DETERMINING SWITCHING OF SLEEP MODE, COMPUTER PROGRAM PRODUCT FOR PERFORMING THE METHOD, AND RECORDING MEDIUM FOR THE COMPUTER PROGRAM PRODUCT - A method for determining switching of the sleep mode for a device is provided. The device and a base station have several connections therebetween. In the determining method, one of the connections is first provided and it is determined whether the connection is realtime or non-realtime. It is then determined whether or not the realtime and non-realtime connections satisfy the condition for entering the sleep mode according to a first condition and a second condition, respectively. If the connection does not satisfy the condition for entering the sleep mode, the device enters the normal mode. If the connection satisfies the condition for entering the sleep mode, then the foregoing steps are repeated till the connections have all been checked. If all of the connections satisfy the condition for entering the sleep mode, the device enters the sleep mode. | 09-16-2010 |