Patent application number | Description | Published |
20080224186 | High Dynamic Range Imaging Cell With Electronic Shutter Extensions - A pixel sensor cell of improved dynamic range comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation. | 09-18-2008 |
20080272399 | PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES - The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input. | 11-06-2008 |
20080272400 | PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES - The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input. | 11-06-2008 |
20080274578 | METHOD OF FORMING A PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES - The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input. | 11-06-2008 |
20090035886 | PREDOPED TRANSFER GATE FOR A CMOS IMAGE SENSOR - A novel CMOS image sensor Active Pixel Sensor (APS) cell structure and method of manufacture. Particularly, a CMOS image sensor APS cell having a predoped transfer gate is formed that avoids the variations of V | 02-05-2009 |
20090141155 | HIGH DYNAMIC RANGE IMAGING CELL WITH ELECTRONIC SHUTTER EXTENSIONS - A pixel sensor cell of improved dynamic range and a design structure including the pixel sensor cell embodied in a machine readable medium are provided. The pixel cell comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation. | 06-04-2009 |
20090217059 | Utilizing Networked Three Dimensional Voltage Regulation Modules (VRM) to Optimize Power and Performance of a Device - A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event. | 08-27-2009 |
20110062240 | DEVICE AND METHOD FOR PROVIDING AN INTEGRATED CIRCUIT WITH A UNIQUE INDENTIFICATION - A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a four wire resistor, thin film resistors, and an inverter pair. A measurement circuit measures a parameter of each cell and is utilized in generating the ID in response thereto. | 03-17-2011 |
20120159203 | UTILIZING NETWORKED 3D VOLTAGE REGULATION MODULES (VRM) TO OPTIMIZE POWER AND PERFORMANCE OF A DEVICE - A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event. | 06-21-2012 |
20130057991 | SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL - Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer. | 03-07-2013 |
20130264608 | Self-Protected Drain-extended metal-oxide-semiconductor Transistor - Device structures, design structures, and fabrication methods for a drain-extended metal-oxide-semiconductor (DEMOS) transistor. A first well of a first conductivity type and a second well of a second conductivity type are formed in a device region. The first and second wells are juxtaposed to define a p-n junction. A first doped region of the first conductivity type and a doped region of the second conductivity type are in the first well. The first doped region of the first conductivity type is separated from the second well by a first portion of the first well. The doped region of the second conductivity type is separated from the second well by a second portion of the first well. A second doped region of the first conductivity type, which is in the second well, is separated by a portion of the second well from the first and second portions of the first well. | 10-10-2013 |
20140127867 | SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL - Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer. | 05-08-2014 |
20150085408 | EOS PROTECTION CIRCUIT WITH FET-BASED TRIGGER DIODES - An integrated circuit is disclosed, including a circuit with a first type of FET having a first breakdown voltage (VBD), resulting from a first set of design and manufacturing process parameters and having VBD tracking characteristics resulting from a second set of design and manufacturing process parameters. The IC may include a trigger device circuit a having a trigger FET that may generate, in response to the supply voltage exceeding a specified maximum, a signal on a trigger device output, causing a clamping device to couple the supply voltage node to the ground, to reduce the supply voltage. The trigger FET may be of a second type having a second VBD less than the first VBD, resulting from modifications to the first set of design and manufacturing process parameters, and VBD tracking characteristics resulting from the second set of design and manufacturing process parameters. | 03-26-2015 |