Patent application number | Description | Published |
20080224129 | FLAT PANEL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain silicon (SGS) crystallization growth region; a capacitor formed in an SGS crystallization seed region; and an OLED electrically connected to the thin film transistor. Further, a length of the channel region of the silicon layer is parallel with the growth direction in the SGS growth region to improve the electrical properties thereof. | 09-18-2008 |
20080246029 | Thin film transistor, organic light emitting display device including the same, and method of manufacturing the organic light emitting display device - A thin film transistor, e.g., for use in an organic light emitting display, may include: a gate insulating layer disposed on a gate electrode located on a substrate; a semiconductor layer, disposed on the gate insulating layer; and a planarization layer disposed on the gate insulating layer, the source and drain electrodes, and the channel area, and having openings exposing parts of the first source and drain areas and the source and drain electrodes, respectively. The semiconductor layer may include: a channel area corresponding to the gate electrode; first source and drain areas doped with an impurity outside the channel area; second source and drain areas, including a metal, outside the first source and drain areas; and source and drain electrodes disposed on the second source and drain areas and exposing the first source and drain areas. A pixel electrode may be disposed in one of the openings. | 10-09-2008 |
20080246037 | Flat display device and method of manufacturing the same - Provided is a flat display device, and more particularly, an active matrix (AM) flat display device having a thin film transistor (TFT). The flat display device includes a substrate, a plurality of TFTs (thin film transistors) provided on the substrate, each TFT comprising an active layer, a source electrode and a drain electrode that contact the active layer, and an ohmic contact layer interposed between the active layer and the source and drain electrodes, and a light emitting device electrically connected to the TFT, wherein the ohmic contact layer and a layer including the source and drain electrodes are formed to have the same pattern. | 10-09-2008 |
20080259668 | Layout structure of bit line sense amplifiers for a semiconductor memory device - A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier. | 10-23-2008 |
20080277666 | Thin film transistor, organic light emitting display device including the same, and method of manufacturing the organic light emitting display device - A thin film transistor (TFT) may include a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, and a semiconductor layer on the gate insulating layer. The semiconductor layer may include a top surface, a channel area aligned in a vertical direction with the gate electrode, a plurality of doped areas proximate to the channel area, and a plurality of non-doped areas. Source and drain electrodes may be on the top surface of the semiconductor layer aligned above respective ones of the plurality of non-doped areas of the semiconductor layer. A planarization layer may be on the gate insulating layer, the source and drain electrodes and the semiconductor layer channel area, and may include a plurality of openings respectively exposing the plurality of doped areas of the semiconductor layer and a portion of the source electrode and the drain electrode. | 11-13-2008 |
20080284326 | Organic light emitting diode display device and method of fabricating the same - Provided is an organic light emitting diode (OLED) display device, including: a substrate; a semiconductor layer on the substrate; a gate insulating layer on the substrate with the semiconductor layer; a gate electrode on a region of the gate insulating layer corresponding to the semiconductor layer and insulated from the semiconductor layer; source and drain electrodes connected to the semiconductor layer; metal layers on the source and drain electrodes, spaced a distance apart from each other, and including nickel; a passivation layer over the gate insulating layer; a first electrode on the passivation layer, and electrically connected to the metal layers; an organic layer on the first electrode; and a second electrode on the organic layer. | 11-20-2008 |
20080303023 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus includes a plurality of pixels arranged on a substrate, each pixel includes: a display region including at least one pixel thin film transistor and an organic light-emitting device electrically connected to the pixel thin film transistor; and a sensor region electrically connected to the display region to affect an image display of the display region. | 12-11-2008 |
20100013745 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device having an electrostatic capacitive type touch panel function with reduced thickness and improved luminance. A display panel of the organic light emitting display device includes a substrate, a display unit having a plurality of pixels on the substrate, and a touch sensing unit on the display unit. The touch sensing unit includes an encapsulation substrate and a capacitive pattern layer on a side of the encapsulation substrate facing the display unit. The capacitive pattern layer has a plurality of openings corresponding in position to the plurality of pixels. | 01-21-2010 |
20100176392 | Thin film transistor and method of manufacturing the same - A TFT includes a substrate, a source electrode and a drain electrode on the substrate, the source and drain electrodes separated from each other, an active layer on the substrate between the source electrode and the drain electrode, a cladding unit on side surfaces of the source electrode and the drain electrode, a gate insulating layer on the substrate, the gate insulating layer overlapping the active layer and the cladding unit, and a gate electrode on the gate insulating layer, the gate electrode overlapping the active layer. | 07-15-2010 |
20100246300 | SEMICONDUCTOR MEMORY DEVICES INCLUDING BURN-IN TEST CIRCUITS - A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed. | 09-30-2010 |
20100302892 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase. | 12-02-2010 |
20110101495 | FUSE BOX FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first and second portions, a second fuse group comprising a plurality of second fuses, arranged in the first direction and having a second cutting axis, each second fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first portion and the second portion, and a third fuse group comprising a plurality of third fuses, wherein each third fuse has either the first cutting axis or the second cutting axis, comprises a first pattern arranged in the first direction and having a first fuse pitch, and a second pattern arranged in a second direction and having a second fuse pitch smaller than the first fuse pitch, and is arranged to bypass the first fuse or the second fuse. | 05-05-2011 |
20110103166 | LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE - A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier. | 05-05-2011 |
20120044734 | BIT LINE SENSE AMPLIFIER LAYOUT ARRAY, LAYOUT METHOD, AND APPARATUS HAVING THE SAME - A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i complementary bit lines are arranged in an i | 02-23-2012 |
20140016424 | METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES - An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device. | 01-16-2014 |