Meil
Christopher Meil, Akron, OH US
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20090052382 | Infrastructure-Based Enabling Indication for Dynamic Frequency Selection in Wireless Networks - A wireless access point selection system. In particular implementations, a method includes receiving a notification that identifies a wireless access point that detects radar on an operating channel and identifies the operating channel; updating neighbor lists of one or more neighboring wireless access points to remove the wireless access point from the neighbor list, where the neighbor list comprises neighbor wireless access points, corresponding operating channels, and corresponding enable indications, where each enable indication indicates if a channel availability check is required before performing active scanning; and transmitting the updated neighbor list to the neighboring wireless access points. In one implementation, a system provides a DFS enable indication to wireless clients so they can know whether a channel availability check is required prior to transmitting. | 02-26-2009 |
20100019947 | ADAPTIVE SAMPLING OF RADIO FREQUENCY CHANNELS FOR RADAR DETECTION - Described in an example embodiment herein is a procedure that comprises sampling one or more channels that are not in use for a short time at certain intervals. In particular embodiments, the interval duration is irregular so as to prevent “out of step” lock with a radar's pulses. During the sampling period, detection events are stored in terms of start time and duration. If potential radar events are detected, the channels are sampled for a longer, second interval to determine whether the detection events are indicative of radar. The length of the sampling period determines the number of samples needed to get an acceptable detection probability. | 01-28-2010 |
Christopher G. Meil, Akron, OH US
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20090201851 | Coordinated Channel Change in Mesh Networks - A coordinated channel change system. In particular implementations, a method includes receiving a prepare-to-change message, wherein the prepare-to-change message indicates instructions to prepare to change channels and includes a designated channel, and forwarding the prepare-to-change message to one or more child nodes. The method also includes receiving a ready-to-change message from the one or more child nodes, and transmitting a change-to-channel message to the one or more child nodes, wherein the change-to-channel message indicates instructions to switch to the designated channel. The method also includes receiving an acknowledgement message from the one or more child nodes, and changing to the designated channel. | 08-13-2009 |
Christopher Graham Meil, Akron, OH US
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20090116411 | Mesh Tree Formation in Wireless Networks - A mesh tree formation system. In particular implementations, a method includes responsive to a selection of a channel potentially bearing a higher priority use, entering a silent state and initiating a channel scan of the selected channel for a period of time. The method also includes, responsive to receipt of an enabling signal, entering a limited transmission state that enables transmission of wireless frames on the selected channel. The method also includes, responsive to termination of the period of time of the channel scan wherein no higher priority use is detected, entering a full transmission state comprising transmission of enabling signals corresponding to the selected channel. | 05-07-2009 |
Doug Meil, Chagrin Falls, OH US
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20140032240 | SYSTEM AND METHOD FOR MEASURING HEALTHCARE QUALITY - In a method for measuring healthcare quality, a plurality of computers operating in parallel receive from a patient dataset representative of patients within a healthcare organization, the patient dataset being distributed across the plurality of computer as subsets of patient datasets. The plurality of computers receive at least one healthcare quality measure definition comprising a numerator and a denominator. The plurality of computers identify, in the subsets of patient datasets, patient data that corresponds to the measure definition. The plurality of computers attribute the identified patient data to at least one provider based on an attribution rule. The plurality of computers calculate at least one healthcare quality measure for the at least one provider, according to the healthcare quality measure definition, based on the attributed patient encounters. The plurality of computers store the at least one calculated healthcare quality measure in a measure dataset. | 01-30-2014 |
Gavin Meil, Round Rock, TX US
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20150347652 | TIMING ANALYSIS OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS - Various implementations of a method, system, and computer program product for executing timing analysis of an asynchronous clock domain crossing are disclosed. In one embodiment, a signal group and a corresponding timing specification are determined for one or more signals of an electronic design. For each of the signals, a clock associated with the signal is renamed based, at least in part, on the signal group associated with the signal. The asynchronous clock domain between a transmit domain and a receive domain is identified in the electronic design based, at least in part, on identifying a signal path associated with one or more renamed clocks that is asynchronous to a clock associated with the receive domain. For each of the one or more renamed clocks, timing analysis is executed across one or more signals associated with the renamed clock at the asynchronous clock domain crossing. | 12-03-2015 |
Gavin B. Meil, Round Rock, TX US
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20150161309 | GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in a register transfer level circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to one or more possible signal states. Determining the input sequence of signal transition representations includes determining that a subsequence of the input sequence of signal transition representations indicates at most one transition within the subsequence of the input sequence. The design tool can determine, based on the indicated component and on the determination that the subsequence indicates at most one transition, an output sequence of signal transition representations derived from the input sequence of signal transition representations. | 06-11-2015 |
20150161310 | CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition. Determining the output sequence includes determining whether signal transition representation(s) of the output sequence indicate an output gated clock waveform. | 06-11-2015 |
20150161311 | CONDITIONAL PHASE ALGEBRA FOR CLOCK ANALYSIS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations. | 06-11-2015 |
20150161312 | STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS - A circuit design checker receives a circuit design. The circuit design can include a first set of one or more logic components in a first clock domain and a second set of one or more logic components in a second clock domain. The clock domain checker identifies a first subset of the second set of one or more logic components that receive one or more asynchronous clock domain crossings. The circuit design is traversed to determine whether a subset of the one or more asynchronous clock domain crossings does not pass through a signal having an attribute indicating that the signal is intended to be part of the one or more asynchronous clock domain crossings. If such a crossing exists, an error is indicated for the circuit design. | 06-11-2015 |
20150161313 | CIRCUIT DESIGN EVALUATION WITH COMPACT MULTI-WAVEFORM REPRESENTATIONS - A design tool can implement phase algebra based design evaluation to efficiently evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. Instead of individual waveforms, the phase algebra based design evaluation employs compact representations of a group or set of waveforms. Phase algebra based evaluation constructs representations of a set of waveforms based on relationships among a devised set of functions that account for the various states of a signal over time, including transitions and glitches. A memorized-transition function, referred to herein as an M-function, indicates signal transitions over time. | 06-11-2015 |
20150161315 | VERIFICATION OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS - Various implementations of a method, system and computer program product receive a circuit model that can include an asynchronous crossing between a first set of one or more logic components in a first clock domain and a second set of one or more logic components in a second clock domain. A shadow network can be constructed that corresponds to the asynchronous crossing, where the shadow network includes at least one of an asynchronous transition detector, an asynchronous sample detector, and a metastability timer. The shadow network can include shadow network signals corresponding to signals of the asynchronous crossing. | 06-11-2015 |
20150269296 | STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS - A circuit design checker receives a circuit design. The circuit design can include a first set of one or more logic components in a first clock domain and a second set of one or more logic components in a second clock domain. The clock domain checker identifies a first subset of the second set of one or more logic components that receive one or more asynchronous clock domain crossings. The circuit design is traversed to determine whether a subset of the one or more asynchronous clock domain crossings does not pass through a signal having an attribute indicating that the signal is intended to be part of the one or more asynchronous clock domain crossings. If such a crossing exists, an error is indicated for the circuit design. | 09-24-2015 |
20150269299 | PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine whether module instances of a register level circuit design share a common usage, each instance being associated with a mapping. Two instances share a common usage if a sequence of signal transition representations received by the first instance can be mapped using a first mapping to the same common sequence of signal transition representations as a mapping of another sequence of signal transition representations received by the second instance using a second mapping. A result sequence of signal transition representations was generated by a previous propagation of the common sequence through the common usage. If the two instances share the common usage, the result sequence is mapped to an output sequence for the second instance using the second mapping. | 09-24-2015 |
Gavin Balfour Meil, Round Rock, TX US
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20090019252 | System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination - A system, method, and program product are provided that identifies a cache set using Translation LookAside Buffer (TLB) attributes. When a virtual address is requested, the method, system, and program product identifies a cache set using buffer attributes. When a virtual address is received, an attempt is made to load the received virtual address from a cache. When the attempt results in a cache miss, a page is identified within a Translation LookAside Buffer that includes the virtual address. A class identifier is then retrieved from the identified page, with the class identifier identifying a cache set that is selected from the cache. | 01-15-2009 |
20090019255 | System and Method for Cache-Locking Mechanism Using Segment Table Attributes for Replacement Class ID Determination - A system, method, and program product are provided that identifies a cache set using Segment LookAside Buffer attributes. When an effective address is requested, an attempt is made to load the received effective address from an L2 cache. When this attempt results in a cache miss, the system identifies a segment within the Segment LookAside Buffer that includes the effective address. A class identifier is retrieved from the identified segment within the Segment LookAside Buffer. This class identifier identifies a cache set selected from the cache for replacement. Data is then reloaded into the cache set of the cache by using the retrieved class identifier that corresponds to the effective address. | 01-15-2009 |
Gavin Balfour Meil, Round Rockl, TX US
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20100115482 | Method for Specifying and Validating Untimed Nets - In accordance with an aspect of the present invention, the method for specifying a portion of a circuit design to be treated as untimed by static timing analysis is performed on the RTL design by means of an attribute annotation. The process is operable to map through to the Physical Design by correlating latches and chip-level nets. This allows the testing process to become closed-loop. Design and simulation time is also greatly reduced due to the accessibility of RTL design. | 05-06-2010 |
Joerg Christian Meil, Weiler DE
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20140171415 | FUNNY CURRENT (IF) INHIBITORS FOR USE IN A METHOD OF TREATING AND PREVENTING HEART DISEASE IN CANINE - The present invention relates to an I | 06-19-2014 |