Patent application number | Description | Published |
20100261304 | Solution-based process for making inorganic materials - Disclosed embodiments provide a solution-based process for producing useful materials, such as semiconductor materials. One disclosed embodiment comprises providing at least a first reactant and a second reactant in solution and applying the solution to a substrate. The as-deposited material is thermally annealed to form desired compounds. Thermal annealing may be conducted under vacuum; under an inert atmosphere; or under a reducing environment. The method may involve using metal and chalcogen precursor compounds. One example of a metal precursor compound is a metal halide. Examples of suitable chalcogen precursor compounds include a chalcogen powder, a chalcogen halide, a chalcogen oxide, a chalcogen urea, a chalcogen or dichalcogen comprising organic ligands, or combinations thereof. Certain disclosed embodiments concern a method for making a solar cell from I-III-VI semiconductors. | 10-14-2010 |
20110120371 | METHOD AND APPARATUS FOR CHEMICAL DEPOSITION - Embodiments of the present system and method are useful for chemical deposition, particularly continuous deposition of thin films. Disclosed systems typically comprise a micromixer and a microchannel applicator. A deposition material or materials is applied to a substrate, such as an oxidized silicon substrate, a flexible substrate useful for forming flexible devices, such as flexible transistors, and combinations of different substrates. Uniform and highly oriented surface morphologies of films deposited using disclosed embodiments are clearly improved compared to films deposited by a conventional batch process. The process can be used to tailor the composition and morphology of the material deposited on a substrate. The present process can be used at low temperatures as a post-deposition, high-temperature annealing step is obviated. | 05-26-2011 |
20110203772 | SYSTEM AND METHOD FOR ENHANCED HEAT TRANSFER USING NANOPOROUS TEXTURED SURFACES - A system and method for performing heat dissipation is disclosed that includes contacting a heat transfer liquid with a heat exchange surface having raised hydrophilic nanoporous nanostructures disposed adjacent a central core upon a substrate. The heat transfer liquid forms a preselected contact angle when placed on the heat exchange surface. The raised nanoporous nanostructures define channels, interconnected pathways, and voids within the nanoporous nanostructures. The nanoporous nanostructures have additional surface irregularities upon the nanostructures themselves. The nanostructures are preferably formed by depositing metal oxides or other materials upon a substrate using a Microreactor Assisted Nanomaterial Deposition (MAND) process. | 08-25-2011 |
20110253629 | Microfluidic devices, particularly filtration devices comprising polymeric membranes, and method for their manufacture and use - The present disclosure describes devices useful for microscale fluid purification, separation, and synthesis devices. Generally, such devices comprise a fluid membrane that separates two or more fluids flowing through plural microchannels operatively associated with the membrane. The fluids can both be liquids, gases, or a liquid and a gas, such as may be used for gas absorption into a liquid. Often, the membrane is a semipermeable membrane, such as might be used with a filtration device, such as a dialyzer. Devices of the present invention can be combined with other microscale devices to make systems. For example, the devices may be coupled with one or more microchemical microfactories, one or more micromixers, one or more microheaters; etc. Examples of devices made according to the present invention included an oxygenator, a dialzyer, microheat exchangers, etc. Particular materials had to be developed for use with certain embodiments of the device disclosed herein. For example, a new composite material was made comprising nanocrystalline cellulose filler and a polysulfone polymeric material. A dialyzer comprising the composite membrane also is disclosed. In order to make the nanocrystalline cellulose-polymer composite, a new method was devised for making an organic dispersion of nanocrystalline cellulose. The method comprised first forming an aqueous dispersion of nanocrystalline cellulose. A mixture was then formed comprising the aqueous dispersion and an organic liquid having a boiling point higher than water. The water was then selectively removed to form a second mixture comprising the nanocrystalline cellulose and the organic liquid. | 10-20-2011 |
20120001356 | APPARATUS AND METHOD FOR CONTINUOUS PRODUCTION OF MATERIALS - Embodiments of a continuous-flow injection reactor and a method for continuous material synthesis are disclosed. The reactor includes a mixing zone unit and a residence time unit removably coupled to the mixing zone unit. The mixing zone unit includes at least one top inlet, a side inlet, and a bottom inlet. An injection tube, or plurality of injection tubes, is inserted through the top inlet and extends past the side inlet while terminating above the bottom outlet. A first reactant solution flows in through the side inlet, and a second reactant solution flows in through the injection tube(s). With reference to nanoparticle synthesis, the reactant solutions combine in a mixing zone and form nucleated nanoparticles. The nucleated nanoparticles flow through the residence time unit. The residence time unit may be a single conduit, or it may include an outer housing and a plurality of inner tubes within the outer housing. | 01-05-2012 |
20120074062 | MICROFLUIDIC DEVICES, PARTICULARLY FILTRATION DEVICES COMPRISING POLYMERIC MEMBRANES, AND METHODS FOR THEIR MANUFACTURE AND USE - The present disclosure describes devices useful for microscale fluid purification, separation, and synthesis. Such devices generally comprise a fluid membrane that separates two or more fluids flowing through plural microchannels operatively associated with the membrane. Often, the membrane is a semipermeable membrane, such as might be used with a filtration device, such as a dialyzer. Devices of the present invention can be combined with other microscale devices to make systems. For example, the devices may be coupled with one or more microchemical microfactories, one or more micromixers, one or more microheaters, etc. Examples of devices made according to the present invention included an oxygenator, a dialyzer, microheat exchangers, etc. | 03-29-2012 |
20120176681 | NANOSTRUCTURED ANTI-REFLECTIVE COATINGS FOR SUBSTRATES - Embodiments of the present system and method are useful for chemical deposition, particularly continuous deposition of anti-reflective films. Disclosed systems typically comprise a micromixer and a microchannel applicator. A deposition material or materials is applied to a substrate to form a nanostructured, anti-reflective coating. Uniform and highly oriented surface morphologies of films deposited using disclosed embodiments are clearly improved compared to films deposited by a conventional batch process. In some embodiments, a scratch-resistant, anti-reflective coating is applied to a polycarbonate substrate, such as a lens. In certain embodiments, an anti-reflective coating is applied to a surface of a solar catalytic microreactor suitable for performing endothermic reactions, where energy is provided to the reactor by absorption of solar radiation. The composition and morphology of the material deposited on a substrate can be tailored. The process can be used at low temperatures as a post-deposition, high-temperature annealing step is obviated. | 07-12-2012 |
20120292246 | MICROFLUIDIC DEVICES, PARTICULARLY FILTRATION DEVICES COMPRISING POLYMERIC MEMBRANES, AND METHOD FOR THEIR MANUFACTURE AND USE - The present disclosure describes devices useful for microscale fluid purification, separation, and synthesis. Such devices generally comprise a fluid membrane that separates two or more fluids flowing through plural microchannels operatively associated with the membrane. Often, the membrane is a semipermeable membrane, such as might be used with a filtration device, such as a dialyzer. Devices of the present invention can be combined with other microscale devices to make systems. For example, the devices may be coupled with one or more microchemical microfactories, one or more micromixers, one or more microheaters, etc. Examples of devices made according to the present invention included an oxygenator, a dialyzer, microheat exchangers, etc. | 11-22-2012 |
20120298037 | MICROCHEMICAL NANOFACTORIES - Embodiments of an apparatus, system, and method for chemical synthesis and/or analysis are disclosed. One embodiment of a disclosed apparatus comprises a laminated, microfluidic structure defining a reactor and a separator. Such apparatuses, or portions thereof, generally have dimensions ranging from about 1 micrometer to about 100 micrometers. To implement synthetic processes, disclosed embodiments of the apparatus generally include at least one unit operation, such as a mixer, a valve, a separator, a detector, and combinations thereof. Individual apparatuses may be coupled both in series and in parallel to form a system for making chemical compounds. An individual apparatus or a system also can be used in combination with known devices and processes. | 11-29-2012 |
20130196053 | FLOW CELL DESIGN FOR UNIFORM RESIDENCE TIME FLUID FLOW - Embodiments of a deposition reactor that compensates for lateral flow variation are disclosed. The reactor has at least one wall defining a deposition chamber comprising a first region and a second region, the wall having a purposely formed curvature defining a height of the deposition chamber. An inlet for a fluid comprising reactants or deposition material is in fluid communication with the deposition chamber. Portions of the fluid flowing through the deposition chamber have a residence time within the deposition chamber that varies by ≦20% across a cross-sectional width of the deposition chamber. The deposition chamber may further comprise an outlet in fluid communication with a third region. The reactor is suitable for depositing material layers having a uniform thickness. Methods of using the reactor also are disclosed. | 08-01-2013 |
20150182936 | CONTINUOUS MICROWAVE-ASSISTED SEGMENTED FLOW REACTOR FOR HIGH-QUALITY NANOCRYSTAL SYNTHESIS - Systems and methods for synthesizing high-quality nanocrystals via segmented, continuous flow microwave-assisted reactor were developed. | 07-02-2015 |
Patent application number | Description | Published |
20100095185 | TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE - Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed. | 04-15-2010 |
20100189168 | SYSTEM, METHOD AND DEVICE FOR AUTONEGOTIATION - Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal. | 07-29-2010 |
20110138250 | TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE - Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed | 06-09-2011 |
20120110421 | TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE - Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed | 05-03-2012 |
20130346666 | TUNNELING PLATFORM MANAGEMENT MESSAGES THROUGH INTER-PROCESSOR INTERCONNECTS - Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity. | 12-26-2013 |
20140019827 | TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE - Techniques to perform forward error correction for an electrical backplane are described. | 01-16-2014 |
20140115223 | DUAL CASTING PCIE INBOUND WRITES TO MEMORY AND PEER DEVICES - Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory write request from a first PCIe device is received at a PCIe root complex and the memory address is inspected to determine whether it falls within an address window defined for dual casting operations. If it does, an IO write request is generated from the inbound system memory write request and sent to a second PCIe device associated with the address window. During a parallel operation, the original inbound system memory write request is forwarded to a system agent configured to receive such write requests. | 04-24-2014 |
20140181394 | DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS - Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor. | 06-26-2014 |
20150113221 | HYBRID INPUT/OUTPUT WRITE OPERATIONS - A first processor receives a write request from an input/output (I/O) device connected to the first processor. The first processor determines whether the write request satisfies an allocating write criterion. Responsive to determining that the write request satisfies the allocating write criterion, the first processor writes data associated with the write request to a cache of the first processor. | 04-23-2015 |
Patent application number | Description | Published |
20110037618 | Driver Safety System Using Machine Learning - A traffic routing display system provides a visual display of the expected state of an upcoming traffic light. In one aspect, the display is an icon colored to correspond to the expected state. In another aspect, the time remaining before the state of a traffic light changes is displayed. The effect that an indicator has on driver behavior is used to determine the type of indicator to provide to the driver. Certain indicators may not be displayed by the system depending on the effect they have on the driver. | 02-17-2011 |
20110037619 | Traffic Routing Using Intelligent Traffic Signals, GPS and Mobile Data Devices - A traffic routing system reduces emissions from commuter and other traffic, eases congestion on roadways, and decreases transit time by use of communications among vehicles and traffic controls, such as traffic lights. In one aspect, a traffic light receives a signal that a vehicle is approaching and in response turns green to allow the vehicle to pass without impairment. In another aspect, a vehicle receives a signal to adjust a current rate of speed to arrive when a traffic signal allows vehicles to pass. In still another aspect, a combination of congestion, emergency traffic, roadwork and similar factors influence proposed routes sent to vehicles. | 02-17-2011 |
20110040621 | Traffic Routing Display System - A traffic routing display system provides a visual display of the expected state of an upcoming traffic light. In one aspect, the display is an icon colored to correspond to the expected state. In another aspect, the intensity of the color varies based on the certainty of the expectation. Another display shows the expected state of the traffic light at various speeds, allowing a driver to slow down for instance if the state of the light is not expected to be different at a slower speed. A speed limit icon is also displayed, and changes color when the speed limit is exceeded. | 02-17-2011 |
20120179358 | SYSTEM AND METHOD FOR AUTOMATED UPDATING OF MAP INFORMATION - The characteristics of two intersecting roadways are compared to determine whether an inference can be made as to whether there are traffic controls (e.g., stop signs) on one of the roadways. If a larger road with characteristically higher speed intersects with a small road with lower speed, the small road is determined to have a stop sign. A map database is updated with the information regarding the inferred traffic control, and that information is then usable for purposes such as trip planning. | 07-12-2012 |
Patent application number | Description | Published |
20090309168 | SELF-ALIGNED SELECTIVE METAL CONTACT TO SOURCE/DRAIN DIFFUSION - A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate formed on the diffusion region, and insulating side walls formed adjacent to the sacrificial gate. A metal gate is formed by etching out the sacrificial gate and filling in the space between the insulating side walls with gate metals. Silicided source and drain contacts are formed over the diffusion region between the side walls of two adjacent aluminum gates. One or more oxide layers are formed over the substrate. Vias are formed in the oxide layers by plasma etching to expose the silicided source and drain contacts, which simultaneously oxidizes the aluminum gate metal. A first metal is selectively formed over the silicided contact by electroless deposition, but does not deposit on the oxidized aluminum gate. | 12-17-2009 |
20110037105 | SELF-ALIGNED SELECTIVE METAL CONTACT TO SOURCE/DRAIN DIFFUSION REGION - A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate formed on the diffusion region, and insulating side walls formed adjacent to the sacrificial gate. A metal gate is formed by etching out the sacrificial gate and filling in the space between the insulating side walls with gate metals. Silicided source and drain contacts are formed over the diffusion region between the side walls of two adjacent aluminum gates. One or more oxide layers are formed over the substrate. Vias are formed in the oxide layers by plasma etching to expose the silicided source and drain contacts, which simultaneously oxidizes the aluminum gate metal. A first metal is selectively formed over the silicided contact by electroless deposition, but does not deposit on the oxidized aluminum gate. | 02-17-2011 |
20120138886 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 06-07-2012 |
20140153881 | TWO-DIMENSIONAL, HIGH-DENSITY OPTICAL CONNECTOR - An optical connector includes a two-dimensional array of lenses to couple optical signals between an optical integrated circuit and an optical fiber. The optical connector has a total-internal-reflection or mirror surface that redirects light between lenses at different surfaces of the optical connector. The lens arrays collimate light directed toward the reflection surface and focuses light received from the reflection surface. The two-dimensional array and prism allows for a low-profile, high-density optical connector based on free space optical light propagation. | 06-05-2014 |
20140326952 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 11-06-2014 |
20150303258 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 10-22-2015 |
Patent application number | Description | Published |
20120251029 | OPTICAL WAVEGUIDE STRUCTURE - Embodiments of the invention describe a multi-segment optical waveguide that enables an optical modulator to be low-power and athermal by decreasing the device length needed for a given waveguide length. Embodiments of the invention describe an optical waveguide that is folded onto itself, and thus includes at least two sections. Thus, embodiments of the invention may decrease the device size of a modulator by at least around a factor of two if the device is folded twofold (device size may be further reduced if the modulator is folded threefold, four-fold, five-fold, etc.). | 10-04-2012 |
20130272649 | OPTICAL CONNECTION TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed. | 10-17-2013 |
20130279845 | FABRICATION OF PLANAR LIGHT-WAVE CIRCUITS (PLCS) FOR OPTICAL I/O - PLC architectures and fabrication techniques for providing electrical and photonic integration of a photonic components with a semiconductor substrate. In the exemplary embodiment, the PLC is to accommodate optical input and/or output (I/O) as well as electrically couple to a microelectronic chip. One or more photonic chip or optical fiber terminal may be coupled to an optical I/O of the PLC. In embodiments the PLC includes a light modulator, photodetector and coupling regions supporting the optical I/O. Spin-on electro-optic polymer (EOP) may be utilized for the modulator while a photodefinable material is employed for a mode expander in the coupling region. | 10-24-2013 |
20140003765 | WAVEGUIDE INTEGRATION ON LASER FOR ALIGNMENT-TOLERANT ASSEMBLY | 01-02-2014 |
20140086527 | VERTICAL LIGHT COUPLER - An optical coupler includes a double-sided planar substrate having a lens manufactured on one side and a mode expander on the other side. The mode expander is coupled to a mirror that redirects light between the mode expander and the lens. The mirror is lithographically aligned with the lens. The substrate is optically transparent to a target wavelength to be used for optical signaling. The lens can be a lens array, in which case there can be a mirror for each lens in the array. The mode expander can couple an optical signal to a planar lightwave circuit (PLC) or other optical circuit. The lens on the optical coupler can interface with a single-mode optical fiber. | 03-27-2014 |
20140177995 | OPTICAL PHOTONIC CIRCUIT COUPLING - Systems and methods may couple on-chip optical circuits to external fibers. An SOI waveguide structure may include mirror structures and tapered waveguides to optically couple optical circuits to fibers in a vertically oriented external connector. The mirror structure(s) may be angularly disposed at the ends of the silicon waveguide structure. An oxide layer may cover a buried oxide layer and the silicon waveguide structure. The tapered waveguide(s) may have a narrow end and a wide end. The narrow end of the tapered waveguide(s) may be disposed above the mirror structures. The tapered waveguide(s) may extend through the oxide layer from the narrow end in a direction perpendicular to the silicon waveguide structure. An external connector may fit over the tapered waveguide(s) and uses a fiber array traveling through a connector body to optically couple to the external fiber. | 06-26-2014 |
20140199015 | SLOTTED Y-COUPLING WAVEGUIDE FOR SLOTTED WAVEGUIDE MODULATOR DEVICE - Embodiments of the present disclosure describe techniques and configurations for decreasing optical loss in a wave-guide of a modulator device. In one embodiment, an apparatus includes a substrate, and a waveguide of a modulator device formed on the substrate, the waveguide having a first portion that is configured to receive light for propagation along the waveguide, a second portion that includes two slots formed in the waveguide that merge into a single slot, the second portion being coupled with the first portion, a third portion that includes the single slot formed in the waveguide, the third portion being coupled with the second portion, a fourth portion that includes another two slots formed in the waveguide, the another two slots branching from the single slot, the fourth portion being coupled with the third portion, and a fifth portion that is configured to output the propagated light, the fifth portion being coupled with the fourth portion. Other embodiments may be described and/or claimed. | 07-17-2014 |
20140203175 | OPTICAL I/O SYSTEM USING PLANAR LIGHT-WAVE INTEGRATED CIRCUIT - Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor. | 07-24-2014 |
20150185895 | INCLINED PHOTONIC CHIP PACKAGE FOR INTEGRATED OPTICAL TRANSCEIVERS & OPTICAL TOUCHSCREEN ASSEMBLIES - An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An inclined paddle sawn flat no-leads (IPSFN) package may be affixed to a cover glass surface along a perimeter of a display. IPSFN packages may incorporate a photo-emitter chip and a photo-detector chip that may be inclined for a desired angle of incidence relative to the cover glass. A CMOS integrated optical transceiver package may include inclined photonic chips and a non-inclined CMOS chip having at least one of a photo-emitter driver, or a photo-detector TIA and/or ADC. A chip package lead frame may include cantilevered paddle tabs amenable to controlled deflection during package assembly. An inclined packaging assembly method may include attaching a chip to a lead frame paddle and form pressing the lead frame to incline the chip to a desired angle before encapsulation. | 07-02-2015 |
20160088740 | INCLINED PHOTONIC CHIP PACKAGE FOR INTEGRATED OPTICAL TRANSCEIVERS & OPTICAL TOUCHSCREEN ASSEMBLIES - An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An inclined paddle sawn flat no-leads (IPSFN) package may be affixed to a cover glass surface along a perimeter of a display. IPSFN packages may incorporate a photo-emitter chip and a photo-detector chip that may be inclined for a desired angle of incidence relative to the cover glass. A CMOS integrated optical transceiver package may include inclined photonic chips and a non-inclined CMOS chip having at least one of a photo-emitter driver, or a photo-detector TIA and/or ADC. A chip package lead frame may include cantilevered paddle tabs amenable to controlled deflection during package assembly. An inclined packaging assembly method may include attaching a chip to a lead frame paddle and form pressing the lead frame to incline the chip to a desired angle before encapsulation. | 03-24-2016 |
Patent application number | Description | Published |
20090003050 | FLOATING BODY MEMORY ARRAY - Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells. | 01-01-2009 |
20090146208 | Independently controlled, double gate nanowire memory cell with self-aligned contacts - A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used. | 06-11-2009 |
20090159975 | INTEGRATION OF PLANAR AND TRI-GATE DEVICES ON THE SAME SUBSTRATE - An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed. | 06-25-2009 |
20100006941 | Intergration of a floating body memory on soi with logic transistors on bulk substrate - A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon. | 01-14-2010 |
20100297838 | INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW - A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device. | 11-25-2010 |
20120267721 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 10-25-2012 |
20130009248 | INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW - A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device. | 01-10-2013 |
20140177625 | ELECTRO-OPTICAL ASSEMBLY INCLUDING A GLASS BRIDGE - Embodiments of the present disclosure provide techniques and configurations for routing signals of an electro-optical assembly using a glass bridge. In one embodiment, an electro-optical assembly includes a laser die having a laser device and a glass bridge electrically coupled with the laser die by one or more interconnect structures, the glass bridge including electrical routing features configured to route electrical signals to the laser die from a transmitter device. Other embodiments may be described and/or claimed. | 06-26-2014 |
20140334768 | LOW COST INTEGRATION OF OPTICAL COMPONENTS IN PLANAR LIGHTWAVE CIRCUITS - Planar lightwave circuits with a polymer coupling waveguide optically coupling a planar waveguide over a first region of a substrate to an optical component, such as a laser, affixed to a second region of the substrate. The coupling waveguide may be formed from a polymer layer applied over the planar waveguide and optical component such that any misalignment between the two may be accommodated by patterning the polymer into a waveguide having a first end aligned to an end of the planar waveguide and a second end aligned to an edge of the optical component. In embodiments, the polymer is photo-definable, such as a negative resist, and may be patterned through direct laser writing. In embodiments, the optical component is a thin film affixed to the substrate through micro-transfer printing. In other embodiments, the optical component is a semiconductor chip affixed to the substrate by flip-chip bonding. | 11-13-2014 |
Patent application number | Description | Published |
20090170279 | METHOD OF PREPARING ACTIVE SILICON REGIONS FOR CMOS OR OTHER DEVICES - A method of preparing active silicon regions for CMOS devices includes providing a structure including a silicon substrate ( | 07-02-2009 |
20100165772 | Self aligned back-gate for floating body cell memory erase - In some embodiments all cells within a word-line of a floating body cell memory are erased. A back-gate of the floating body cell memory is self-aligned with the word line, and the erasing is performed using a back-gate bias. Other embodiments are described and claimed. | 07-01-2010 |
20110298098 | EXPITAXIAL FABRICATION OF FINS FOR FINFET DEVICES - A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall. | 12-08-2011 |
20140015021 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 01-16-2014 |
20150179650 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 06-25-2015 |
Patent application number | Description | Published |
20100002707 | DYNAMIC UPDATE OF ROUTE TABLE - A method and apparatus for dynamically modifying routing information in an interconnect architecture without quiescence is herein described. Each agent/node holds routing information regarding target agents/nodes in an interconnect architecture, which may include routing preferences. When a node is to be hot removed, it generates port disable messages to neighbors. The neighbors disable a port the disable message is received on and generates a completion message back to the not to be removed. The node to be removed continues to route messages until it receives a completion; at which time it disables a corresponding node. When all nodes are disabled the device may be removed. Other nodes in the interconnect architecture learn of an agent removal through use of return cycles when messages reach dead ends during attempted routing of cycles. Furthermore, hot addition of a node includes broadcasting of an enable message to enable nodes for routing to the added node. | 01-07-2010 |
20110286458 | DYNAMIC UPDATE OF ROUTE TABLE - A method and apparatus for dynamically modifying routing information in an interconnect architecture without quiescence is herein described. Each agent/node holds routing information regarding target agents/nodes in an interconnect architecture, which may include routing preferences. When a node is to be hot removed, it generates port disable messages to neighbors. The neighbors disable a port the disable message is received on and generates a completion message back to the not to be removed. The node to be removed continues to route messages until it receives a completion; at which time it disables a corresponding node. When all nodes are disabled the device may be removed. Other nodes in the interconnect architecture learn of an agent removal through use of return cycles when messages reach dead ends during attempted routing of cycles. Furthermore, hot addition of a node includes broadcasting of an enable message to enable nodes for routing to the added node. | 11-24-2011 |
20130279622 | METHOD AND SYSTEM OF REDUCING POWER SUPPLY NOISE DURING TRAINING OF HIGH SPEED COMMUNICATION LINKS - A method and system to reduce the power supply noise of a platform during the training of high speed communication links. In one embodiment of the invention, the device has logic to stagger a bit lock pattern for each of one or more communication links and scramble a training sequence for each of the one or more communication links. By doing so, it removes the need for anti-noise circuits and in turn, reduces the silicon area and power of the devices. Further, by having the logic in the physical layers to facilitate the training of the communication links, it eliminates the need to redesign the package of the devices to shift the resonant frequencies. | 10-24-2013 |
20140281276 | METHOD, APPARATUS, AND SYSTEM FOR LOW LATENCY COMMUNICATION - A method, apparatus, computer program product, and computer readable medium to perform receipt of a snoop notification indicating a write to a memory address associated with a cache, determination that the snoop notification signifies receipt of a message based, at least in part, on the memory address, and performance of an operation based, at least in part, on the message is disclosed. | 09-18-2014 |
Patent application number | Description | Published |
20080206502 | FLEXIBLE BARRIER MEMBRANES EMPLOYING POLY (HYDROXY AMINO ETHERS) - A multi-layer composite has at least one elastomer layer and at least one barrier layer. In various embodiments, the composite contains at least two elastomer layers alternating with at least two barrier layers. In other embodiments, the composite comprises at least ten alternating barrier and elastomer layers. The barrier layer is made of an amorphous polymer, and is provided in the form of a film. Preferably, the amorphous polymer film has a gas transmittance rate (GTR) of less than 40 cc·mil/m | 08-28-2008 |
20090297744 | GEL REDUCTION IN BLENDS OF THERMOPLASTIC POLYURETHANE AND HYDROXYL FUNCTIONAL POLYMERS - Gas barrier layers and composites contain a low gel sheet produced from a composition containing a thermoplastic polyurethane (TPU), a hydroxyl functional copolymer, and a gel reducing additive. The gel reducing additive has functional groups that can react with isocyanate groups to reduce gel formation during the processing of blends of urethane containing polymers and hydroxyl functional polymers. Multilayer composites containing the low gel sheets can be made into inflatable membranes for containing an inflationary gas. In a particularly preferred embodiment, the membranes are used as bladders of cushioning devices in the soles of shoes, particularly athletic shoes. | 12-03-2009 |
20140250609 | METHOD FOR DYEING GOLF BALLS AND DYED GOLF BALLS - A golf ball of a first color is dyed to a second color with an anionic or nonionic disperse dye. Either or both of a pigmented coating layer or an optional clear coating layer on the pigmented coating layer comprises a member selected from the group consisting of polyurethanes, polyureas, polyamides, and combinations thereof, which can be dyed by the anionic or nonionic disperse dye. | 09-11-2014 |
20140250611 | ACID DYEING OF POLYURETHANE MATERIALS - A polyurethane is dyed with an aqueous solution of an acid dye compound, a quaternary ammonium compound selected from soluble tetrabutylammonium compounds and tetrahexylammonium compounds, and, optionally, an water-soluble organic solvent. | 09-11-2014 |
20140256468 | METHOD FOR DYEING GOLF BALLS AND DYED GOLF BALLS - A golf ball of a first color is dyed to a second color with an anionic or nonionic disperse dye. Either or both of the cover or an optional clear coating layer on the cover comprises a member selected from the group consisting of polyurethanes, polyureas, polyamides, and combinations thereof, which can be dyed by the anionic or nonionic disperse dye. | 09-11-2014 |
20140259329 | DECORATIVE FOAM AND METHOD - Decorative foamed articles are prepared from foamed pellets, beads, particles, or other articles of a thermoplastic elastomer infused with a supercritical fluid in a pressurized container, then rapidly depressurized and heated either by immersion in a heated fluid that can rapidly heat the article or with infrared or microwave radiation to heat and foam the pellets, beads, particles, or other articles that are then molded into the articles. The pellets are dyed with a nonionic or anionic dye one of: (1) before being infused with the supercritical fluid, (2) during being infused with the supercritical fluid by a nonionic or anionic dye dissolved or dispersed in the supercritical fluid, which optionally comprises a polar liquid, (3) during immersion in the heated fluid, where the heated fluid contains the dye, or (4) after being foamed. | 09-18-2014 |
20140259753 | MODIFIED THERMOPLASTIC ELASTOMERS FOR INCREASED COMPATIBILITY WITH SUPERCRITICAL FLUIDS - A foamed article is made by infusing the article of thermoplastic elastomer including a nonpolar component with a supercritical fluid, then removing the article from the supercritical fluid and either (i) immersing the article in a heated fluid or (ii) irradiating the article with infrared or microwave radiation. | 09-18-2014 |
20140272379 | PROCESS FOR FOAMING THERMOPLASTIC ELASTOMERS - A foamed article is made by infusing the article of thermoplastic elastomer with a supercritical fluid, then removing the article from the supercritical fluid and either (i) immersing the article in a heated fluid or (ii) irradiating the article with infrared or microwave radiation. | 09-18-2014 |
20140275306 | ARTICLE WITH CONTROLLED CUSHIONING - Pellets, beads, particles, or other pieces of a thermoplastic elastomer having a maximum size in at least one dimension of 10 mm or less (collectively, “pellets”) are infused with a supercritical fluid in a pressurized container, then rapidly depressurized and heated either by immersion in a heated fluid or with infrared or microwave radiation to foam the pellets The pellets are prepared with at least two different densities. Pellets with different densities, thermoplastic elastomer compositions, or foam response rates are placed in different areas of a mold. The mold is filled with pellets, then the pellets are molded into a part. The part has areas of different density as a result of the placement of pellets of different density. | 09-18-2014 |
20160075113 | MEMBRANES AND USES THEREOF - Membranes and methods for producing them are disclosed. The membranes comprise a core layer comprising a composite of alternating thermoplastic polyurethane (TPU) and barrier microlayers, and they comprise at least one cap layer that is bonded to the core layer or a structural layer. In some embodiments, at least the cap layer comprises a polydiene polyol-based TPU. The membrane may further comprise a rubber layer bonded to the cap layer. | 03-17-2016 |