Prins, US
Casey Prins, Hamilton, MI US
Patent application number | Description | Published |
---|---|---|
20110023721 | AIR FILTRATION DEVICE - An air filtration device comprises a housing assembly having at least one first mounting surface and having at least one air outlet, a blower positioned in the housing assembly for blowing air towards the at least one outlet, and a motor for driving the blower. At least one air intake has at least two intake mounting surfaces which are the same as each other and the same as the first mounting surface, wherein the air intake is attached to the housing assembly at one of the first mounting surfaces. At least one of the two intake mounting surfaces is positioned at an acute angle with respect to the other of the two intake mounting surfaces. Also, a muffler can be positioned adjacent the at least one air outlet. The muffler defines an opening operatively connected to the air outlet and the opening has a first cavity having a first volume, a second cavity having a second volume, and a third cavity having a third volume. The second cavity is between the first cavity and the third cavity, and the second volume is greater than both the first volume and the third volume. | 02-03-2011 |
Christiaan Prins, San Francisco, CA US
Patent application number | Description | Published |
---|---|---|
20150373050 | Aggregation of asynchronous trust outcomes in a mobile device - Systems and techniques are provided for aggregation of asynchronous trust outcomes in a mobile device. Trust levels may be determined from the signals. Each trust level may be determined independently of any other trust level. Each trust level may be determined based on applying to the signals heuristics, mathematical optimization, decisions trees, machine learning systems, or artificial intelligence systems. An aggregated trust outcome may be determined by aggregating the trust levels. Aggregating the trust levels may include applying heuristics, mathematical optimization, decisions trees, machine learning systems, or artificial intelligence systems to the trust levels, and wherein the aggregated trust outcome; and sending the aggregated trust outcome to be implemented by the enabling, disabling, or relaxing of at least one security measure based on the aggregated trust outcome. | 12-24-2015 |
Doug Prins, Laguna Hills, CA US
Patent application number | Description | Published |
---|---|---|
20110228601 | MLC SELF-RAID FLASH DATA PROTECTION SCHEME - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 09-22-2011 |
20120266032 | MLC Self-RAID Flash Data Protection Scheme - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 10-18-2012 |
20120266052 | MLC Self-RAID Flash Data Protection Scheme - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 10-18-2012 |
20120272106 | MLC Self-RAID Flash Data Protection Scheme - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 10-25-2012 |
Douglas A. Prins, Morgan Hill, CA US
Patent application number | Description | Published |
---|---|---|
20090172258 | Flash memory controller garbage collection operations performed independently in multiple flash memory groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold. | 07-02-2009 |
20090172499 | Patrol function used in flash storage controller to detect data errors - A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors. | 07-02-2009 |
Douglas Alan Prins, Laguna Hills, CA US
Patent application number | Description | Published |
---|---|---|
20120324148 | SYSTEM AND METHOD OF PROTECTING METADATA FROM NAND FLASH FAILURES - Methods and systems are disclosed for protecting metadata from NAND flash failures. With data striped across multiple flash memory chips, the flash memory multiple chips may store multiple copies of metadata (and potentially ECC). The metadata stored in the multiple copies on the flash memory chips may be different from one another. For example, on a particular chip, a first copy of metadata is stored and a second copy of metadata is stored, with the second copy being a redundant copy of the metadata stored on a different chip. In this way, if one of the chips fails, a copy of the failed chips metadata is stored on another of the chips, and may be accessed. | 12-20-2012 |
20120324277 | SYSTEM AND METHOD FOR DETECTING COPYBACK PROGRAMMING PROBLEMS - Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page. | 12-20-2012 |
Etienne Peter Prins, Sarasota, FL US
Patent application number | Description | Published |
---|---|---|
20130026692 | C frame clamping device having non-rotating anvils - A clamping device having a C shaped frame and anvils which cannot rotate while applying a clamping force is disclosed. One anvil is affixed to the C shaped frame while the second anvil is mounted to a drive tube which telescopes within a guide tube fixed to the frame. The conformal shapes of the guide and drive tubes prevent rotation as compressive force is applied to a work piece placed between the two anvils. | 01-31-2013 |
Garrett P. Prins, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20140271205 | TURBINE BLADE PIN SEAL - A gas turbine engine turbine disk assembly includes a turbine disk, turbine blades, and pin seals. Each turbine blade includes a platform with a pressure side seal slot extending into a pressure side of the platform and a suction side seal slot extending into a suction side of the platform. The pressure side seal slot and the suction side seal slot are each angled between three and ten degrees in the radial direction relative to the axis of the turbine disk. The pin seal includes a cylindrical shape and is located within a seal slot formed from the pressure side seal slot and the suction side seal slot of adjacent turbine blades. | 09-18-2014 |
20140271206 | TURBINE BLADE WITH A PIN SEAL SLOT - A gas turbine engine turbine disk assembly includes a turbine disk, turbine blades, and pin seals. Each turbine blade includes a platform with a pressure side seal slot extending into a pressure side of the platform and a suction side seal slot extending into a suction side of the platform. The pressure side seal slot and the suction side seal slot are each angled between three and ten degrees in the radial direction relative to the axis of the turbine disk. The pin seal includes a cylindrical shape and is located within a seal slot formed from the pressure side seal slot and the suction side seal slot of adjacent turbine blades. | 09-18-2014 |
John R. Prins, Seattle, WA US
Patent application number | Description | Published |
---|---|---|
20090200410 | MODULAR GRINDING CORE AND GRINDING DEVICES INCORPORATING THE SAME - A modular grinding core includes a housing configured to be operatively installed in a variety of external grinding devices, a rasp support member having a coupling adapter configured to be operatively coupled to an actuation mechanism of a first external grinding device at a first time and to an actuation mechanism of a second external grinding device at a second time after being removed from the first external grinding device. The rasp support member includes a receptacle configured to removably receive any one of a variety of rasps. The rasp support member is configured to reciprocate in response a force exerted by the external grinding device. The modular grinding core further includes a grind block member resisting displacement of the food items or spices away from the rasp support member, and an adjustment mechanism allowing a user to adjust a gap between the grind block and rasp support members. | 08-13-2009 |
Lincoln Dale Prins, Cedar Rapids, IA US
Patent application number | Description | Published |
---|---|---|
20160044747 | MODULAR ANTI-FOG DEVICES - A modular anti-fog device for attachment to a wearable optical device such as glasses, goggles, and the like. The anti-fog device includes a translucent carrier configured to hold a conductive element. The conductive element is electrically coupled to a power source. The conductive element provides resistive heating upon passage of electrical current through the conductive element. The translucent carrier includes an adhering layer enabling the anti-fog device to be attached to an optical device so as to provide the optical device with anti-fog functionality. | 02-11-2016 |
Lloyd Alfred Prins, Tulsa, OK US
Patent application number | Description | Published |
---|---|---|
20110252941 | Fix-mounted Guitar Bridge - Disclosed is a guitar bridge having a body comprised of a main base plate and a tone device. The bridge main base plate mounts flush to the guitar main body upper surface by a plurality of coupling screws. The bridge tone device extends perpendicular to the underside surface of main base plate into and out of contact from a tone chamber formed into the top surface of the guitar main body. Strings are threaded over a plurality of saddles then through a plurality of holes formed in the bridge main base plate. Strings continue through a plurality of holes formed through the guitar main body where the strings terminating ball ends are anchored against the underside surface of guitar main body. | 10-20-2011 |
Michael Henry Prins, Hudsonville, MI US
Patent application number | Description | Published |
---|---|---|
20090205267 | STAIR STRINGER ASSEMBLY - A stringer assembly includes a support element, a plurality of brackets and a plurality of alignment elements. The brackets are connected to the support element, and each bracket includes a rise indicator corresponding to a desired rise dimension and a run indicator corresponding to a desired run dimension. The alignment elements align the rise or run indicator on one of the brackets with the other of the rise or run indicator on an adjacent one of the brackets to space the brackets at a desired rise and run. The brackets each include a tread flange and a riser flange, such that a tread and a riser can be directly connected to each bracket. The brackets may include cutouts for a temporary tread system. | 08-20-2009 |
20090266955 | GARAGE DOOR BRACKET - A bracket assembly attaches a garage door track to the ceiling joists or another structural support. In one embodiment, an upper bracket includes an upper horizontal element, a lower horizontal element, and at least one support element extending between the upper and lower horizontal elements. The upper element may include a ceiling flange that is angled approximately ninety degrees from the remainder of the bracket. A vertical bracket member attaches to the upper horizontal element, the lower horizontal element and the garage door track. The bracket can reduce installation time, labor, and the potential for error from the typical installation arrangement and method by reducing the number of cuts that the installer must make, and by reducing the number of fasteners that are needed. | 10-29-2009 |
20110271612 | STAIRWAY TREAD AND RISER ASSEMBLY - A stairway assembly includes a tread and riser panel attached together by a uniquely designed gusset to form a tread and riser assembly that can be integrally installed on the stringers. In one embodiment, a first portion of the gusset includes a first attachment structure connected to the lower surface of the tread, and a second portion of the gusset has a second attachment structure connected to the lower surface of the riser. The first portion of the gusset extends at an angle from the second portion, with the side edge of the riser overlapping and facing the upper surface of the tread, and said tread side edge faces said gusset. The gusset may include an elongated slot that forms a line of weakening in the gusset. The gusset may be bent about the line of weakening to move the tread and riser into the final position in which the tread is perpendicular to the riser. | 11-10-2011 |
Robert M. Prins, Pacific Palisades, CA US
Patent application number | Description | Published |
---|---|---|
20150202291 | COMBINATIONS OF CHECKPOINT INHIBITORS AND THERAPEUTICS TO TREAT CANCER - A combination treatment regimen including one or more cycles and/or doses of a checkpoint inhibitor and a therapeutic, either sequentially, in either order, or substantially simultaneously, can be more effective in treating cancer in some subjects and/or can initiate, enable, increase, enhance or prolong the activity and/or number of immune cells, the efficacy of anti-tumor immune responses or a medically beneficial response by a tumor. | 07-23-2015 |
20150273033 | COMBINATIONS OF CHECKPOINT INHIBITORS AND THERAPEUTICS TO TREAT CANCER - The present disclosure arises at least in part from the seminal recognition that a combination treatment regimen including one or more cycles and/or doses of a checkpoint inhibitor and a therapeutic, either sequentially, in either order, or substantially simultaneously, can be more effective in treating cancer in some subjects and/or can initiate, enable, increase, enhance or prolong the activity and/or number of immune cells, or a medically beneficial response by a tumor. | 10-01-2015 |
Sonia L. Prins, Reno, NV US
Patent application number | Description | Published |
---|---|---|
20110070949 | BUTTON PANEL AND LIGHT ASSEMBLY FOR USE WITH GAMING MACHINES - A gaming machine includes a button panel having a front surface, wherein at least a portion of the front surface is an optically restrictive material, and a plurality of light devices aligned relative to the optically restrictive material. The gaming machine also includes a controller coupled to the plurality of light devices, wherein the controller is configured to control at least one of an order of illumination for at least a portion of the plurality of light devices and a duration of illumination for at least a portion of the plurality of light devices. | 03-24-2011 |
Steve Prins, Fairview, TX US
Patent application number | Description | Published |
---|---|---|
20140327082 | SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CONTACT PATTERNS IN A BIT CELL ARRAY - An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps. | 11-06-2014 |
20150029773 | CONTEXT PROTECTION FOR A COLUMN INTERLEAVED MEMORY - A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits. | 01-29-2015 |
20160049410 | SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CONTACT PATTERNS IN A BIT CELL ARRAY - An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps. | 02-18-2016 |
Steven L. Prins, Fairview, TX US
Patent application number | Description | Published |
---|---|---|
20090096055 | METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SELECTIVE EPITAXIAL SILICON POST STI ETCH - An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width. | 04-16-2009 |
20090098702 | Method to Form CMOS Circuits Using Optimized Sidewalls - A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed by depositing a conformal layer of spacer material on the isolation hardmask and performing an anisotropic etch. The isolation sidewall spacers reduce the exposed substrate width during the subsequent STI trench etch process, leading to a reduced STI trench width. A method of forming the isolation sidewall spacers of a material that is easily removed from the isolation hardmask to provide an exposed shoulder width on the substrate defined by the sidewall thickness is also disclosed. | 04-16-2009 |
20100261298 | CURVATURE REDUCTION FOR SEMICONDUCTOR WAFERS - A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization. | 10-14-2010 |
20100261353 | WAFER PLANARITY CONTROL BETWEEN PATTERN LEVELS - A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present. | 10-14-2010 |
Steven Lee Prins, Richardson, TX US
Patent application number | Description | Published |
---|---|---|
20090101983 | Method of Achieving Dense-Pitch Interconnect Patterning in Integrated Circuits - Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible for metal interconnect lines, thus preventing dense rectilinear grid configurations for contacts and vias. The instant invention is an integrated circuit, and a method of fabricating an integrated circuit, wherein metal interconnect lines are formed on a minimum pitch possible using a photolithographic printer. Contacts and vias are arranged to provide connections to components and metal interconnect lines, as required by the integrated circuit, in configurations that are compatible with the minimum pitch for contacts and vias, including semi-dense arrays. | 04-23-2009 |
Steven Lee Prins, Fairview, TX US
Patent application number | Description | Published |
---|---|---|
20120302059 | ALIGNMENT TO MULTIPLE LAYERS - A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction. | 11-29-2012 |
20150187768 | POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE IN DUAL STRESS LINER PROCESS FLOW - An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule. | 07-02-2015 |
20150325472 | ALIGNMENT TO MULTIPLE LAYERS - A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction. | 11-12-2015 |
Taylor J. Prins, Milpitas, CA US
Patent application number | Description | Published |
---|---|---|
20160118132 | Low Impact Read Disturb Handling - A storage device system receives read commands from a host device and maintains a read disturb count for distinct zones of each of a plurality of non-volatile memory blocks in the storage device. The read disturb count for each zone corresponds to read operations performed in the zone and in predefined memory portions neighboring the zone. In accordance with a determination that the read disturb count for any zone satisfies predefined threshold criteria, the storage device performs a validation operation on one or more memory portions corresponding to that zone. If the validation operation is unsuccessful, the storage device resets the read disturb count for the zone and initiates a refresh operation on at least a portion of the corresponding block. If the validation operation is successful, the storage device resets the read disturb count for the zone that satisfied the predefined threshold criteria, and forgoes initiating the refresh operation. | 04-28-2016 |
Timothy George Prins, Solon, OH US
Patent application number | Description | Published |
---|---|---|
20120251663 | DOUGH TARGETING FOR ENHANCED MICROWAVE REHEATING - The invention relates to a method of improving the organoleptic properties of a baked dough product which is to be reheated with microwaves, by targeting and positioning first and second dough portions in the dough product that respond differently to microwave reheating after baking to achieve optimal consumer experience and quality benefits. The baked dough product obtainable by the method is another embodiment of the invention. | 10-04-2012 |