Haymes
Alan Haymes, Redbridge Essex GB
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20100236052 | DEVICE AND METHOD FOR FORMING A BARRIER TO A SMOKING ARTICLE - A device for and a method form a barrier comprised of a distributed zone of fluid in a filter of a smoking article. The device includes a container for a fluid which forms a wet impact barrier when inserted into the smoking article, and a delivery feature communicating between the container and an outlet of the delivery feature, for transfer of the fluid to filter of the smoking article. The delivery feature is formed by a tube of significantly lesser diameter than the diameter of the smoking article. The combination of container and delivery feature provides for placement of a defined quantity of fluid at a predetermined location within the smoking article, such as by injection through a side wall of the filter in the vicinity of the filter/tobacco boundary. | 09-23-2010 |
Charles L. Haymes, Yorktown Heights, NY US
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20110019533 | Network Element Bypass in Computing Computer Architecture - A method and apparatus in accordance with the present invention provides monitoring a self-adjusting multi-tier processing system. At least one computing resource of one of the tiers of the self-adjusting multi-tier processing system is dynamically bypassed based on at least one predetermined criterion, wherein dynamically bypassing energizes or de-energizes a bypass control switch that operates to route data between tiers of the system in a manner that excludes the at least one computing resource. | 01-27-2011 |
Charles L. Haymes, Fair Lawn, NJ US
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20090199070 | DATA TRANSMISSION SYSTEM AND METHOD OF CORRECTING AN ERROR IN PARALLEL DATA PATHS OF A DATA TRANSMISSION SYSTEM - A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths. | 08-06-2009 |
20120117413 | METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) - A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided. | 05-10-2012 |