Patent application number | Description | Published |
20120299300 | TURBINE GENERATOR SYSTEM - A turbine generator system is operable to provide electric power to an electric network connected thereto, and includes a turbine generator apparatus and an output module. The turbine generator apparatus includes a turbine rotor provided with a plurality of blades and rotatable to output a mechanical torque, and a generator coupled to the turbine rotor and to be driven by the mechanical torque to generate driving electric power having a system frequency. The output module is electrically connected to the turbine generator apparatus for converting the driving electric power into output electric power to be provided to the electric network. The generator includes a mechanical filter that is operable, when the turbine generator system has a fault, to resonate in a specified frequency that is based on the system frequency to make the blades of the turbine rotor less sensitive to electromagnetic torque disturbance attributed to the fault. | 11-29-2012 |
20130010898 | OFDM BEAMFORMER, AND A SIGNAL RECEIVING SYSTEM INCORPORATING THE SAME - An OFDM beamformer of a signal receiving system receives multiple frequency-domain sample signal vectors each transformed from arrival signals received by a corresponding antenna element of an antenna array, and includes: multiple signal splitters each splitting a corresponding frequency-domain sample signal vector into a data signal subvector and a pilot signal subvector based on predetermined position information; a weight generator generating an estimated auto-correlation matrix and an estimated cross-correlation vector based on the data signal subvectors, the pilot signal subvectors, and a reference pilot signal vector associated with a desired user, and generating an optimal weight vector based on the estimated auto-correlation matrix and the estimated cross-correlation vector; and a combining unit combining, based on the optimal weight vector, serial data signals converted from each data signal vector by a corresponding parallel-to-serial converter to generate an estimated data symbol output corresponding to the desired user. | 01-10-2013 |
20130011022 | Method and Computer Program Product for Extracting Feature Vectors from a Palm Image - A method for extracting feature vectors from a palm image includes the steps of: determining a palm contour in the palm image, and labeling pixels on the palm contour as contour pixels in order along the palm contour; determining a rotation angle of the palm contour relative to a coordinate system; obtaining corrected contour pixels to offset the rotation angle; determining a plurality of feature points from the corrected contour pixels; obtaining a plurality of sub-images from the palm image with reference to the feature points, one of the sub-images corresponding to a palm center and another one of the sub-images corresponding to a corresponding palm finger; and determining the feature vectors with reference to the sub-images, each of the feature vectors corresponding to a corresponding one of the sub-images. | 01-10-2013 |
20130028310 | EVALUATION DEVICE FOR PROVIDING A TRANSCEIVER SYSTEM WITH TRANSCEIVING PERFORMANCE INFORMATION THEREOF - An evaluation device provides a transceiver system with performance information. The transceiver system models channels between a transmitter and a receiver thereof using Nakagami distribution with a fading parameter. The evaluation device includes a setting module, a computing module and an output module. The computing module is operable, based upon the fading parameter, an average SNR of the channels, a number of transmit antennas and a number of receive antennas, to estimate an average output SNR, a bit error rate and an outage probability related to signals received by the receiver. The output module is operable to provide the transceiver system with the average SNR and the estimated information as the performance information. | 01-31-2013 |
20130188672 | Evaluation device and method for providing a transceiver system with performance information thereof - An evaluation device is configured to provide a transceiver system with performance information thereof. The transceiver system models a channel between a transmitter and a receiver thereof using Nakagami distribution with a fading parameter. The evaluation device includes a setting module operable to set an average signal-to-noise rate (SNR) for the channel between the transmitter and the receiver, a computing module operable to estimate a symbol error rate related to a signal received by the receiver from the transmitter based upon the fading parameter and the average SNR, and an output module operable to provide the average SNR and the symbol error rate as the performance information of the transceiver system. | 07-25-2013 |
Patent application number | Description | Published |
20120184869 | ELECTROENCEPHALOGRAM SIGNAL PROCESSING METHOD - An electroencephalogram signal processing method includes a recording step, a retrieving step, a removing step and a synthesizing step. The recording step retrieves EEG signal components of a testee via a plurality of electrodes, wherein the EEG signal components serve as an input signal. The retrieving step filters the input signal to obtain a predetermined frequency band signal, and subtracts the predetermined frequency band signal from the input signal to obtain a difference signal. The removing step performs an independent component analysis operation between the difference signal and a separating matrix to obtain an analysis signal, generates a separating pseudo inverse and an independent analysis signal, and performs a matrix operation between the separating pseudo inverse and the independent analysis signal to obtain a corrected signal. The synthesizing step adds the corrected signal and the predetermined frequency band signal together to obtain an output signal. | 07-19-2012 |
20120303350 | ANALYSIS METHOD FOR TURBINE-GENERATOR TORSIONAL VIBRATIONS AFFECTED BY POWER TRANSMISSION SYSTEM - An analysis method for turbine-generator torsional vibrations affected by power transmission system, which is processed by a computer system with a simulation software, is proposed. This analysis method comprises: building structures of a first system model and a second system model to respectively simulate a first system and a second system; building detailed models of the first and second system model; and analyzing the detailed models of the first and second system model in frequency- and time-domain. | 11-29-2012 |
20130204818 | MODELING METHOD OF NEURO-FUZZY SYSTEM - A modeling method of neuro-fuzzy system including a rule-defining process and a network-building process is disclosed. The rule-defining process divides a plurality of training data into a plurality of groups to accordingly define a plurality of fuzzy rules, and the network-building process constructs a fuzzy neural network based on the fuzzy rules obtained by the rule-defining process. The provided modeling method of neuro-fuzzy system is capable of building a neuro-fuzzy system extremely similar to an original function that generates training data of the neuro-fuzzy system. | 08-08-2013 |
Patent application number | Description | Published |
20110319033 | Evaluation Device and Method for Providing a Transceiver System with Performance Information Thereof - An evaluation device is adapted for providing a transceiver system with performance information thereof. The transceiver system models a channel between a transmitter and a receiver thereof using Nakagami distribution with a fading parameter. The evaluation device includes a threshold value computing module, a signal-to-noise ratio (SNR) setting module, a probability computing module, and an output module. The threshold value computing module is operable to compute a threshold value based upon a given capacity. The SNR setting module is operable to set an average SNR for the channel between the transmitter and the receiver of the transceiver system. The probability computing module is operable, based upon the fading parameter, the average SNR and the threshold value, to compute an outage probability of the transceiver system corresponding to the given capacity. The output module is operable to provide the transceiver system with the average SNR and the outage probability. | 12-29-2011 |
20120128051 | Evaluation Device for Providing a Transceiver System with Performance Information Thereof - An evaluation device is adapted for providing a transceiver system with performance information thereof. The transceiver system includes a transmitter and at least one receiver, and models a channel between the transmitter and the receiver using Nakagami distribution with a fading parameter. The evaluation device includes a signal-to-noise ratio (SNR) setting module, an error rate computing module, and an output module. The SNR setting module is operable to set an average SNR for the channel between the transmitter and the receiver of the transceiver system. The error rate computing module is operable, based upon the fading parameter, the average SNR and a number of the receiver, to compute a bit error rate over the channel between the transmitter and the receiver. The output module is operable to provide the transceiver system with the average SNR and the bit error rate as the performance information of the transceiver system. | 05-24-2012 |
20120129466 | Evaluation Device and Method for Providing a Transceiver System with Performance Information Thereof - An evaluation device is adapted for providing a transceiver system with performance information thereof. The transceiver system models a channel between a transmitter and a receiver thereof using Nakagami distribution with a fading parameter. The evaluation device includes a signal-to-noise ratio (SNR) computing module, a capacity computing module, and an output module. The SNR computing module is operable to set an average SNR for the channel between the transmitter and the receiver, and to compute an expected value and variance of an effective SNR of the transceiver system according to the fading parameter and the average SNR. The capacity computing module is operable to compute an outage capacity of the transceiver system based upon the expected value and the variance of the effective SNR and a transmission outage parameter. The output module is operable to provide the transceiver system with the average SNR and the outage capacity. | 05-24-2012 |
Patent application number | Description | Published |
20090117750 | Methods of Forming a Semiconductor Device - The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å. | 05-07-2009 |
20100124823 | NOVEL METHOD FOR REMOVING DUMMY POLY IN A GATE LAST PROCESS - A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle. | 05-20-2010 |
20100240204 | METHODS FOR FORMING METAL GATE TRANSISTORS - A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier. | 09-23-2010 |
20110081774 | METHODS FOR A GATE REPLACEMENT PROCESS - A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process. | 04-07-2011 |
20110124134 | END-CUT FIRST APPROACH FOR CRITICAL DIMENSION CONTROL - A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer. | 05-26-2011 |
20110250725 | METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK - A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure. | 10-13-2011 |
20110312145 | SOURCE AND DRAIN FEATURE PROFILE FOR IMPROVING DEVICE PERFORMANCE AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 12-22-2011 |
20120001238 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device. | 01-05-2012 |
20120083088 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 04-05-2012 |
20120094448 | METHOD OF FABRICATING EPITAXIAL STRUCTURES - A method for fabricating an integrated device is disclosed. The disclosed method provides improved formation selectivity of epitaxial films over a pre-determined region designed for forming an epi film and a protective layer preferred not to form an epi, polycrystalline, or amorphous film thereon during an epi film formation process. In an embodiment, the improved formation selectivity is achieved by providing a nitrogen-rich protective layer to decrease the amount of growth epi, polycrystalline, or amorphous film thereon. | 04-19-2012 |
20120273847 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate. | 11-01-2012 |
20130149821 | Methods for a Gate Replacement Process - A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process. | 06-13-2013 |
20130323891 | Integrated Circuit Device with Well Controlled Surface Proximity and Method of Manufacturing Same - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 12-05-2013 |
20140106479 | End-Cut First Approach For Critical Dimension Control - A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer. | 04-17-2014 |