Patent application number | Description | Published |
20110217687 | EXAMINATION SYSTEM AND METHOD THEREOF - An examination system and an examination method are disclosed. The examination method includes: generating a first test data by a host device, in which the first test data has a plurality of questions; rearranging the questions of the first test data in order to generate a second test data; and sending the second test data to a corresponding examination device for taking the examination. An anti-cheating module is provided for detecting distances between the examination devices or detecting a deviation angle of a character image of the examinee. When the distance is less than a predetermined value or the deviation angle is greater than a predetermined value, an anti-cheating signal is then generated for avoiding cheating actions. | 09-08-2011 |
20110296530 | ELECTRONIC READING APPARATUS AND THE DATA SECURITY METHOD THEREOF - Present invention relates to an electronic reading apparatus with data security and anti-theft functions. The electronic reader apparatus has a code input unit for receiving a security code, and a code determining unit for determining an authenticity of the security code. When no security code, no authentic security code or even no operational signal has been received during the predetermined periods of time, a central control unit may stop a power supply unit from outputting power in order to turn off the electronic reader apparatus and clear the image shown on a display unit. As such, a content of sensitive or confidential data stored in the electronic reading apparatus may not be intruded. | 12-01-2011 |
20120013983 | DISPLAY DEVICE - A display device includes a transparent active element array substrate and a color display layer. The transparent active element array substrate has a first surface and a second surface opposite to the first surface. The color display layer disposed on the first surface of the transparent active element array substrate. | 01-19-2012 |
20120061650 | Transistor Structure - A transistor structure comprises a patterned N-type transparent oxide semiconductor formed over a substrate as a base, and a patterned p-type organic polymer semiconductor formed on the patterned N-type transparent oxide semiconductor comprising a first portion and a second portion so that the patterned N-type transparent oxide semiconductor and the first portion and the second portion of the patterned p-type organic polymer semiconductor form heterojunctions therebetween respectively, wherein the first portion of the patterned p-type organic polymer semiconductor is used as an emitter, and the second portion of the patterned p-type organic polymer semiconductor is used as a collector. | 03-15-2012 |
20120068172 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting display device includes a substrate, a transparent electrode layer, a source/drain layer, an IGZO semiconductor layer, a first insulating layer, a gate layer, a second insulating layer and an organic light emitting diode. The organic light-emitting display device can have a simplified manufacturing process. In addition, the present invention also provides a method for manufacturing the organic light-emitting display device. | 03-22-2012 |
20120070984 | METHOD FOR FORMING ELECTRODE STRUCTURE - In a method for forming an electrode structure in a display device, e.g. a source, drain or gate electrode or a pixel electrode, a photoactive conductive layer, which includes conductive material containing photoactive material, is formed above a substrate of the display device. The photoactive conductive layer is then patterned with a photo-mask and partially removed without the presence of a photo-resist to form the electrode structure. | 03-22-2012 |
20120135588 | METHOD FOR PATTERNING A METAL LAYER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES BY USING THE SAME - Disclosed herein is a method for patterning a metal layer, which includes the following steps. A substrate having a metal layer thereon is provided. A patterned conductive polymeric layer is formed on the metal layer, wherein a portion of the metal layer is exposed by the patterned conductive polymeric layer. The substrate having the patterned conductive polymer layer is disposed in an electrolytic cell, so that the exposed portion of the metal layer is immersed in the electrolytic solution of the electrolytic cell. The anode of the electrolytic cell is electrically coupled to the patterned conductive polymeric layer, while the cathode of the electrolytic cell is immersed in the electrolytic solution. Sequentially, an electrical potential is applied across the anode and the cathode to perform an electrolysis reaction so that the exposed portion of the metal layer is dissolved in the electrolytic solution. | 05-31-2012 |
20120138919 | PHOTO SENSING UNIT AND PHOTO SENSOR THEREOF - A photo sensing unit used in a photo sensor includes a photo sensing transistor, a storage capacitor, and a switching transistor. The photo sensing transistor receives a light signal for inducing a photo current correspondingly, and a source and a gate thereof are respectively coupled to the first signal source and the second signal source. The storage capacitor stores electrical charges induced by the light signal, one terminal thereof is coupled to drain of the photo sensing transistor, and another terminal thereof is coupled to a low voltage. The switching transistor is controlled by the second signal source for outputting a readout signal from the storage capacitor to the signal readout line. The threshold voltage of the photo transistor is higher than that of the switching transistor. | 06-07-2012 |
20120175607 | THIN FILM TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A thin film transistor (TFT) structure includes a substrate, a gate, a gate dielectric layer, a source, a drain and a transparent material layer. The gate is formed on the substrate; the gate dielectric layer is formed on the gate; the source and the drain are formed on the gate dielectric layer; and the transparent material layer has a channel area and an insulating area, and the channel area is disposed on a portion of the gate dielectric layer located between the source and the drain; and the insulating area is disposed on the channel area, the source and the drain. | 07-12-2012 |
20120194898 | E-PAPER DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes a substrate, a driving circuit, an E-paper display layer and a protective coating layer. The driving circuit is arranged on the substrate. The E-paper display layer is disposed on and driven by the driving circuit. The protective coating layer is coated on and in contact with the E-paper display layer. The protective coating layer can provide protection and better optical performance, and it is advantageous to the manufacturing method to overcome the problems such as bubbles and low light transmittance occurring in the conventional manufacturing method. | 08-02-2012 |
20120256316 | SIGNAL LINE STRUCTURE OF A FLAT DISPLAY - The signal line structure is disposed between a gate driver and a display area of a display. The signal line structure includes a substrate, first metal layers, a first insulation layer, second metal layers, a second insulation layer and third metal layers. The first metal layers are arranged in parallel and toward a first direction in the substrate. The first insulation layer is disposed in the substrate and covers the first metal layers. The second metal layers are disposed on the positions of the first insulation layer corresponding to the first metal layers. The second insulation layer is disposed on the second metal layers and the first insulation layer. The third metal layers are disposed on the positions corresponding to the second metal layers in the second insulation layer. The distance between two adjacent second metal layers is less than that between two adjacent first metal layers. | 10-11-2012 |
20130076601 | DRIVING SUBSTRATE AND DISPLAY APPARATUS USING THE SAME - An exemplary driving substrate includes a substrate, a plurality of first and second signal transmission lines, a first insulation layer and a plurality of switch devices. The first signal transmission lines are disposed on the substrate, and each includes a first line segment(s) and a first connecting segment(s). The first insulation layer is disposed between each first line segment and each first connecting segment, and each first connecting segment is electrically connected to the adjacent first line segment(s) through an opening(s) of the first insulation layer. The second signal transmission lines are disposed on the substrate and electrically insulated and intersected with the first signal transmission lines thereby defining a plurality of pixel regions on the substrate. The switch devices are respectively disposed in the pixel regions, and each is electrically connected to corresponding first and second signal transmission lines. The driving substrate has better reliability. | 03-28-2013 |
20130175520 | THIN FILM TRANSISTOR - A thin film transistor suitable for being disposed on a substrate is provided. The thin film transistor includes a gate electrode, an organic gate dielectric layer, a metal oxide semiconductor layer, a source electrode and a drain electrode. The gate electrode is disposed on the substrate. The organic gate dielectric layer is disposed on the substrate to cover the gate electrode. The source electrode, the drain electrode and the metal oxide semiconductor layer are disposed above the organic gate dielectric layer, and the metal oxide semiconductor layer contacts with the source electrode and the drain electrode. Because the channel layer of the thin film transistor is a layer of metal oxide semiconductor formed at a lower temperature, thus the thin film transistor can be widely applied into various display applications such as flexible display devices. | 07-11-2013 |
Patent application number | Description | Published |
20120140783 | Wavelength-Tunable Laser Source Apparatus - A wavelength-tunable laser source apparatus is provided, having first and second Fabry-Perot laser diodes, a tunable bandpass filter and an optical coupler. One of the first and second Fabry-Perot laser diodes outputs a light source to be injected into the other of the first and second Fabry-Perot laser diodes. The tunable bandpass filter is coupled between the first and second Fabry-Perot laser diodes to adjust the light source to a desired wavelength mode. The optical coupler couples the light source, wherein a gain resonance cavity is formed by the first and second Fabry-Perot laser diodes, the tunable bandpass filter and the optical coupler, and the optical coupler outputs light in the gain resonance cavity to serve as a laser source. | 06-07-2012 |
20120328231 | FIBER SENSING SYSTEMS AND FIBER SENSING METHODS - A fiber sensing system is provided, including a plurality of ring structures, an optical coupler and a switching unit. Each of the ring structures has at least one fiber sensor to receive and reflect a light source signal. The optical coupler is directly connected to the ring structures thereby injecting the light source signal into the ring structures to form a plurality of loops. The switching unit is disposed in a central office having two output terminals coupled to the ring structure respectively by the optical coupler, thereby forming a first path and a second path in the loops, such that the light source signal is injected into the first path and the second path sequentially by the switching unit. | 12-27-2012 |
20130343760 | SYSTEM AND METHOD FOR OPTICAL TRANSMISSION - A system and a method for optical transmission are provided. The system includes a power combiner, a laser light source, a negative chirp modulator, and multiple transmission units. Each transmission unit corresponds to a frequency band and generates a first output signal in the frequency band based on orthogonal frequency-division multiplexing (OFDM). The frequency bands are not overlapped with each other. The power combiner is coupled to each transmission unit. The power combiner combines each of the first output signals to generate a second output signal. The negative chirp modulator is coupled to the power combiner and the laser light source. The negative chirp modulator performs negative chirp modulation on the laser light source with the second output signal to generate a light signal and outputs the light signal to an optical fiber. | 12-26-2013 |
20140056589 | VLC MODULATION SYSTEM AND METHOD THEREOF - A VLC (Visible Light Communication) modulation system and method thereof, which includes a visible light generating device and a visible light receiving device. The visible light generating device includes a visible light emitting module and an arbitrary waveform generator. The arbitrary waveform generator further includes a first finite impulse response filtering unit, a pre-distortion amount control unit, and a second finite impulse response filtering unit. | 02-27-2014 |
Patent application number | Description | Published |
20130270702 | COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer. | 10-17-2013 |
20140061913 | Aluminum Interconnection Apparatus - An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy, a first alloy layer formed underneath the metal structure and a first barrier layer formed underneath the first alloy layer, wherein the first barrier layer is generated by a reaction between the first alloy layer and an adjacent dielectric layer during a thermal process. | 03-06-2014 |
20140235050 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. | 08-21-2014 |
20140327141 | COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A copper interconnect structure in a semiconductor device comprises a dielectric layer having sidewalls and a surface defining an opening in the dielectric layer. The copper interconnect structure also comprises a barrier layer deposited on the sidewalls and the surface of the dielectric layer defining the opening. The copper interconnect structure further comprises a barrier/seed mixed layer deposited on the barrier layer. The copper interconnect structure additionally comprises an adhesive layer deposited on the barrier/seed mixed layer. The copper interconnect structure also comprises a seed layer deposited on the adhesive layer. | 11-06-2014 |
20140367857 | Method and Apparatus for Back End of Line Semiconductor Device Processing - Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). A barrier layer comprising a bottom part and a side part is formed within an opening for a metal contact, wherein the bottom part comprises a graphene material, the side part comprises an amorphous carbon material and covers a sidewall of the opening, and the bottom part and the side part are formed at a same time. A capping layer comprising a first part and a second part is formed on a dielectric layer and a metal contact, wherein the first part comprises a graphene material, the second part of the capping layer comprises an amorphous carbon material on the dielectric layer, and the first part and the second part are formed at a same time. | 12-18-2014 |
Patent application number | Description | Published |
20110315865 | METAL VOLUME SOURCE CALIBRATION PHANTOM AND CALIBRATING METHOD THEREOF - A metal volume source calibration phantom includes a container, a plurality kinds of metal plates stacked up inside the container, and at least one slab of radioactive source, each of which is disposed between the adjacent metal plates and includes a plurality of radionuclides. By means of inserting different numbers of the plurality kinds of metal plates inside the container, it is capable of obtaining the metal volume source calibration phantoms with different densities. In addition, a method for calibrating the metal volume source calibration phantom is also provided, which starts by the step of providing the metal calibration phantoms with different densities by inserting different numbers of a plurality kinds of metal plates and at least one slab of radioactive source into the container, and then detecting counting efficiency with respect to the metal volume calibration phantoms having different densities by a waste curie monitor so as to establish the correlation between density and counting efficiency. | 12-29-2011 |
20140042309 | IN-SITU CALIBRATION SYSTEM AND METHOD FOR RADIATION MONITORS - By using a scintillation surveymeter with good calibration performance evaluation for a secondary standard radiation field, and a working standard part obtaining an ambient dose equivalent rate, in cooperation with a portable irradiator, and an irradiator lifter, a laser range finder and a laser locator of a relevant radiation source, in-situ calibration is capable of being performed on fixed, or large-scale, or continuous monitoring type radiation monitors to be calibrated stationed in nuclear power plants, nuclear medical departments, and other nuclear facility operating institutions. Moreover, a time-efficient and effective in-situ calibration method is further provided, which can be performed based upon a standard calibration field that is achieved using a portable | 02-13-2014 |
Patent application number | Description | Published |
20090256183 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
20090256184 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
20110121373 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 05-26-2011 |
20110266601 | Single Gate Semiconductor Device - A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor. | 11-03-2011 |
20120025352 | BIPOLAR JUNCTION TRANSISTOR DEVICES - A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other. | 02-02-2012 |
Patent application number | Description | Published |
20100157158 | SIGNAL PROCESSING APPARATUSES CAPABLE OF PROCESSING INITIALLY REPRODUCED PACKETS PRIOR TO BUFFERING THE INITIALLY REPRODUCED PACKETS - A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit. | 06-24-2010 |
20100158042 | PACKET PROCESSING APPARATUS AND METHOD CAPABLE OF GENERATING MODIFIED PACKETS BY MODIFYING PAYLOADS OF SPECIFIC PACKETS IDENTIFIED FROM RECEIVED PACKETS - A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets. | 06-24-2010 |
20100162089 | PACKET PROCESSING APPARATUS AND METHOD CAPABLE OF GENERATING MODIFIED PACKETS BY MODIFYING PAYLOADS OF SPECIFIC PACKETS IDENTIFIED FROM RECEIVED PACKETS - A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets. | 06-24-2010 |
20100272186 | TRANSPORT STREAM PROCESSING SYSTEM AND RELATED METHOD THEREOF - A transport stream processing system capable of recording and playing back a transport stream carrying a plurality of transport stream packets is provided, and includes: a first memory unit storing a plurality of sets of control words; a packet identifier filter acquiring a set of control words according to a packet identifier value of a transport stream packet and configuring an indicator to indicate whether the transport stream packet is for a recording or a playback operation; a second memory unit storing a plurality of data structures, wherein each data structure corresponds to an index number of each set of control words; and a processor determining whether the recording or playback operation for the transport stream packet is performed for the transport stream packet according to the indicator, retrieving a data structure according to the index number corresponding to the acquired set of control words and performing the operation accordingly. | 10-28-2010 |
Patent application number | Description | Published |
20090074310 | IMAGE DATA COMPRESSION METHOD - An image data compression method is disclosed. Firstly, check a variance between a first image data and a second image data for comparing the variance with a threshold value. When the variance is smaller than a threshold value, compare the first image data with the second image data to generate a motion vector and compress the motion vector. Then calculate the first image data and the second image data according to the motion vector so as to get an offset value of the motion vector. Next, encode the offset value of the motion vector, compress the offset value of the motion vector, and encode as well as compress the first image data. Thus the compression ratio is improved and image distortion is avoided. | 03-19-2009 |
20090103673 | SIGNAL POWER COMBINER WITH DYNAMIC PHASE COMPENSATION - The present invention relates to a signal power combiner with dynamic phase compensation, which uses a plurality of phase shifters to receive a first input signal and a second input signal, and shift the phases of the first and second input signals. A detection unit detects the phases of the first input signal and the second input signal, produces a compensation signal, and transmits to the plurality of phase shifters for shifting the phases of the first input signal and the second input signal. A combiner receives the compensated first and second input signals, combines the first input signal and the second input signal, and produces an output signal. Thereby, the transmission quality of signals is improved. | 04-23-2009 |
20110245604 | CAPSULE ENDOSCOPE AND CAPSULE ENDOSCOPY SYSTEM - The present invention provides a capsule endoscope and a capsule endoscopy system. The capsule endoscope includes a power supply module, an image function module and a power control module. The image function module is configured to capture the image outside the capsule endoscope. The power control module is electrically connected to the power supply module and includes an electronic switch. The power control module controls the electronic switch according to a predetermined condition to control the electric power provided from the power supply module to the image function module. By this configuration, the power control module is able to suspend the power supply until the capsule endoscope reaches the specific location in the digestive tract, and then starts the power supplying to enable the successive image inspection of the capsule endoscope. Therefore, the electric power is conserved to enable the inspection of the end portion of digestive system of the capsule endoscope. | 10-06-2011 |
20110245611 | EXPANDABLE CAPSULE ENDOSCOPE AND EXPANDABLE CAPSULE ENDOSCOPY SYSTEM - The present invention provides an expandable capsule endoscope and an expandable capsule endoscopy system thereof. The expandable capsule endoscope is swallowed to provide the image inspection function of the digestive tract. The expandable capsule endoscope includes an endoscopy function module, an expandable structure and an expansion function module. The endoscopy function module is configured to capture the image outside the expandable capsule endoscope. The expandable structure covers the endoscopy function module. The expansion function module is disposed inside the expandable structure and configured to control the expansion of the expandable structure according to an expansion signal. Therefore, the expandable capsule endoscope can expand itself to a volume to stretch and flatten the wrinkles or folds of the intestine wall so as to facilitate image capturing and maintain the orientation of the expandable capsule endoscope. | 10-06-2011 |
20120143005 | Expandable Capsule Endoscope - An expandable capsule endoscope includes a shell, a membrane and a bag. Inside the shell are a first compartment and a second compartment, and the membrane is disposed between the first compartment and the second compartment. The bag is connected outside the shell. There is a first substance and a second substance respectively disposed in the first compartment and the second compartment. When the membrane is ruined and broken by a heating energy, the first substance and the second substance react to produce a gas filling the bag. The expandable capsule endoscope is applicable to examine an organ with wider diameters and advantageous to capture images of the organ thus providing better reliability and utility. | 06-07-2012 |
Patent application number | Description | Published |
20110306194 | FABRICATION METHOD OF SELF-ALIGNED TRENCHED POWER SEMICONDUCTOR STRUCTURE - A fabrication method of a self-aligned power semiconductor structure is provided. Firstly, a trenched polysilicon gate is formed in a silicon substrate. Then, a self-aligned polysilicon extending structure is formed on the trenched polysilicon gate. A width of the self-aligned polysilicon extending structure is smaller than that of the trenched polysilicon gate. Thereafter, the self-aligned polysilicon extending structure is oxidized to form a silicon oxide protruding structure on the trenched polysilicon gate. Then, a first spacer is formed on a sidewall of the silicon oxide protruding structure to define a source contact window. | 12-15-2011 |
20110316077 | POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region. | 12-29-2011 |
20120267713 | POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region. | 10-25-2012 |
20120322217 | FABRICATION METHOD OF TRENCHED POWER SEMICONDUCTOR DEVICE WITH SOURCE TRENCH - A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region. | 12-20-2012 |
20130292761 | TRENCH POWER MOSFET AND FABRICATION METHOD THEREOF - An exemplary embodiment of the present disclosure illustrates a trench power MOSFET which includes a base, a plurality of first trenches, and a plurality of second trenches. The base has an active region and a termination region, wherein the termination region surrounds the active region. The plurality of first trenches is disposed in the active region. The plurality of second trenches is disposed in the termination region, wherein the second trenches extend outward from the active region side. The second trenches have isolation layers and conductive material deposited inside, in which the isolation layers are respectively disposed in the inner surface of the second trenches. The disclosed trench power MOSFET having the second trenches disposed in the termination region can increase the breakdown voltage thereof while minimize the termination region area thereby reduce the associated manufacturing cost. | 11-07-2013 |
20140042534 | TRENCHED POWER MOSFET WITH ENHANCED BREAKDOWN VOLTAGE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region. | 02-13-2014 |
20140120670 | TRENCHED POWER MOSFET WITH ENHANCED BREAKDOWN VOLTAGE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region. | 05-01-2014 |
20140349456 | TRENCH POWER MOSFET STRUCTURE FABRICATION METHOD - A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by on implantation method for moderate the electric field distribution and decreasing the conduction loss. | 11-27-2014 |
20140361362 | POWER TRANSISTOR HAVING A TOP-SIDE DRAIN AND FORMING METHOD THEREOF - A power transistor having a top-side drain and a forming method thereof are provided. Firstly, a body layer is formed. An epitaxial layer is subsequently formed on the body layer. Then a gate trench is formed in the body layer and the epitaxial layer. Afterward, a gate structure is formed in the gate trench. Then, a doped drain layer is formed within the epitaxial layer. Next, a source is formed in contact with the body layer. Lastly, a drain is formed in contact with the dope drain layer. The structure and forming method disclosed can through arranging the drain at the top of the power transistor integrate with the newly high performance packaging design structure. Accordingly, the efficiency of the power transistor can be greatly enhanced. | 12-11-2014 |
Patent application number | Description | Published |
20120133807 | IMAGE CAPTURE DEVICE - An image capture apparatus comprises an image sensor array including a plurality of image sensors arranged in a two-dimensional (2-D) array and an analog-to-digital converter (ADC) array including a plurality of ADCs arranged in a 2-D array. The image sensor array is divided into a plurality of sub-arrays, each of which includes at least two image sensors. The image sensor array is vertically stacked on the ADC array. Each ADC corresponds to one sub-array of image sensors and is coupled to process signals output by the image sensors in the corresponding sub-array. | 05-31-2012 |
20120154654 | IMAGE PICKUP APPARATUS AND METHOD THEREOF - An image pickup apparatus and a method thereof are provided. The apparatus includes a sensor array and an ADC array. The sensor array includes M×N sensor blocks SB(i,j). The sensor block includes P×Q image sensing elements Se(x,y). The ADC array is located at another side of the illuminated side of the sensor array. The ADC array includes M×N ADCs ADC(i,j). The ADC(i,j) coupled to the sensor block SB(i,j) obtains the image data Data(x,y) from the image sensing element Se(x,y) of the sensor block SB(i,j). The ADC(i,j) evaluates the gain G(x,y) based on the position of the image sensing element Se(x,y). The compensated image data Datacom(x,y) can be outputted and Datacom(x,y)=Data(x,y)×G(x,y). The image pickup apparatus could improve the optical shading problem. | 06-21-2012 |
20120205520 | IMAGE SENSOR AND SENSING METHOD THEREOF - An image sensor including a pixel array is provided. The pixel array includes R×S sub-pixel arrays. The sub-pixel array includes P×Q pixels. Each pixel includes a photodiode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The gate of the second transistor is coupled to a row control signal. The second source/drain electrode of the second transistor is coupled to a column control signal. The gate electrode of the third transistor is coupled to a reset signal. The second source/drain electrode of the third transistor is coupled to a column voltage reset signal. The gate electrode of the fifth transistor is coupled to a row select signal. The sub-pixel array uses the row control signal, the column control signal, the column voltage reset signal, and the row select signal to select an output the sensing signal of one of the pixels. | 08-16-2012 |
20130265066 | PIXEL ARRAY MODULE WITH SELF-TEST FUNCTION AND METHOD THEREOF - A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided. | 10-10-2013 |
Patent application number | Description | Published |
20090184316 | Method to extract gate to source/drain and overlap capacitances and test key structure therefor - A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region. | 07-23-2009 |
20110022997 | METHOD FOR CONJECTURING EFFECTIVE WIDTH AND EFFECTIVE LENGTH OF GATE - A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first gate design length is provided. Second, an intrinsic gate channel capacitance and an edge capacitance of the first design gate are respectively obtained by calculation. Then a size error, i.e. a width error or a length error is predicted by means of the intrinsic gate channel capacitance and of the edge capacitance to calculate a calculated inversion capacitance and a predicted size deviation. Later, the size error is repeatedly predicted to minimize the predicted size deviation and to optimize the size error to obtain an optimized size error. Afterwards, the effective size of the gate are conjectured by means of the optimized size error. | 01-27-2011 |
20120164355 | LIQUID CRYSTAL COMPOUNDS AND COMPOSITIONS AND LIQUID CRYSTAL DISPLAYS AND PHOTOELECTRIC DEVICES COMPRISING THE COMPOUNDS AND COMPOSITIONS - A liquid crystal compound of Formula (1) is provided. | 06-28-2012 |
20120197593 | Parameter extraction method for semiconductor device - A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel capacitance per unit area. | 08-02-2012 |
Patent application number | Description | Published |
20100075480 | STI STRESS MODULATION WITH ADDITIONAL IMPLANTATION AND NATURAL PAD SIN MASK - A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation. | 03-25-2010 |
20130093026 | SELECTIVE FIN-SHAPING PROCESS USING PLASMA DOPING AND ETCHING FOR 3-DIMENSIONAL TRANSISTOR APPLICATIONS - A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin. | 04-18-2013 |
20130119482 | FIN FIELD EFFECT TRANSISTORS AND METHODS FOR FABRICATING THE SAME - The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric. | 05-16-2013 |
20130221491 | FIN FIELD-EFFECT TRANSISTORS HAVING CONTROLLED FIN HEIGHT AND METHOD OF MAKING - A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited. | 08-29-2013 |
20150035017 | Contact Structure of Semiconductor Device - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle. | 02-05-2015 |
Patent application number | Description | Published |
20090284398 | SENSING APPARATUS AND SCAN DRIVING METHOD THEREOF - A sensing apparatus and a scan driving method thereof are provided. The sensing apparatus includes first and second electrodes, a sensing element array, first and second electrode scan driving circuits and a control circuit. The sensing element array outputs at least one first inductive voltage after being touched. The first electrode scan driving circuit sequentially scans and drives the first electrodes, wherein the driven first electrode is set to a high level output state and the first electrode not being driven is set to a low level output state or a grounding state. The second electrode scan driving circuit sequentially scans and drives the second electrodes, wherein the driven second electrode is set to high impedance (input) state, and the second electrode not being driven is set to a low level output state or the grounding state. The control circuit controls the first and second electrode scan driving circuits. | 11-19-2009 |
20100037709 | ARRAY TYPE PRESSURE SENSING APPARATUS AND PRESSURE MEASUREMENT METHOD USING THE SAME - An array type pressure sensing apparatus suitable for multi-touch sensing and pressure quantification for gray scale identification is provided. The array type pressure sensing apparatus includes a plurality of first axes, a plurality of second axes, a plurality of piezoresistive units, a third axis, a plurality of standard resistors and a control unit. The second axes are disposed crisscross with the first axes, and there is one piezoresistive unit disposed on the cross between one first axis and one second axis. The third axis is disposed crisscross with the first axes, and there is one standard resistor on the cross between one first axis and the third axis. A pressure measurement method implemented using the array type pressure apparatus is also provided. The pressure measurement method is a gray scale identification method by pressure quantification of a linear piezo-resistive system. | 02-18-2010 |
20110140930 | Touch Apparatus, Transparent Scan Electrode Structure, and Manufacturing Method Thereof - A touch apparatus, a transparent scan electrode, a geometric electrode structure and a manufacturing method thereof are disclosed. The transparent scan electrode structure comprises a first transparent scan electrode, a second transparent scan electrode and an isolative layer. The first transparent scan electrode comprises a first resistance region and a second resistance region. A resistance value of the second resistance region is higher than that of the first resistance region. The isolative layer is disposed between the first transparent scan electrode and the second transparent scan electrode. | 06-16-2011 |
20150029491 | APPARATUS FOR MICROFLUID DETECTION - A apparatus for microfluid detection for detecting a sample fluid including a plurality of magnetic particles is provided. The apparatus for microfluid detection includes a microfluidic chip and a magnetic generating module. The microfluidic chip includes a substrate and microfluidic channels, wherein the sample fluid is carried by a carry surface of the substrate. The magnetic generating module is adapted for providing a positioning magnetic field and a surrounding magnetic field. The magnetic module controls to move the sample fluid and change a distribution of the magnetic particles in the sample fluid through the positioning magnetic field and the surrounding magnetic field. | 01-29-2015 |
Patent application number | Description | Published |
20100085268 | ANTENNA - An antenna having a number of operating frequencies includes a feed element, a ground element, and a number of conductive antenna tracks. The conductive antenna tracks extend outward from the feed element and return back to the ground element. When the conductive antenna tracks are located in a same plane, areas defined by the conductive antenna tracks are not overlapped with one another. When parts of the conductive antenna tracks are located in different planes, multiple frequency bands are formed respectively by multiple resonant frequencies corresponding to the conductive antenna tracks. | 04-08-2010 |
20140085158 | COMMUNICATION DEVICE AND ANTENNAS WITH HIGH ISOLATION CHARACTERISTICS - A communication device includes a system circuit board, a ground plane, a first antenna, a second antenna, a first metal element, and a second metal element. The ground plane is disposed on the system circuit board. The first metal element is substantially located between the first antenna and the second antenna. The first metal element is coupled to the ground plane such that a system ground plane is formed. The second metal element is adjacent to the first metal element and substantially located between the first antenna and the second antenna. The second metal element is coupled to the system ground plane. The first antenna, the second antenna, and the first metal element are substantially located at an edge of the system circuit board. | 03-27-2014 |
20150070239 | ANTENNA - The invention provides an antenna for a wireless device, e.g., a cellular phone for wireless mobile telecommunication. The antenna includes a conductive feed strip and a conductive ground component. The ground component is for connecting a ground voltage, and comprises a portion along a surface of the device. The feed strip has a feed port for relaying a feed signal, and does not physically contact the ground component, so as to feed the ground component by noncontact electrical coupling, instead of physical contact. | 03-12-2015 |
Patent application number | Description | Published |
20130069143 | TRENCH TYPE POWER TRANSISTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate. | 03-21-2013 |
20140110766 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure has a second portion with an appendage on one side of the second portion and extruding along the longitudinal direction of the second portion. Moreover the semiconductor structure also has a gate line longitudinally parallel to the second portion, wherein the length of the gate line equals to the longitudinal length of the second portion. | 04-24-2014 |
20140131838 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. Semiconductor units are arranged on a substrate. A material layer is formed on the semiconductor units. A first patterned mask layer is formed on the semiconductor units. The first patterned mask layer has a mask opening corresponding to a portion of the semiconductor units and exposing the material layer. A portion of the material layer exposed by the mask opening is removed to remain a portion of the material layer on a sidewall of each of the semiconductor units exposed by the mask opening to form spacer structures. | 05-15-2014 |
20140140131 | THREE DIMENSIONAL GATE STRUCTURES WITH HORIZONTAL EXTENSIONS - A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure. | 05-22-2014 |
20140264898 | 3-D IC Device with Enhanced Contact Area - A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors. | 09-18-2014 |
Patent application number | Description | Published |
20090195327 | TRANSMITTING RADIO FREQUENCY SIGNAL IN SEMICONDUCTOR STRUCTURE - A semiconductor device for transmitting a radio frequency signal along a signal line includes a signal line that extends along a principal axis. On one side of the signal line is a first dielectric, and on the opposite side of the signal line is a second dielectric. First and second ground lines are proximate to the first and second dielectrics, respectively, and the ground lines are approximately parallel to the signal line. The device has a transverse cross-section that varies along the principal axis. | 08-06-2009 |
20110260819 | CONTINUOUSLY TUNABLE INDUCTOR WITH VARIABLE RESISTORS - An integrated tunable inductor includes a primary inductor having a plurality of inductor turns, at least one closed loop eddy current coil proximate the primary inductor, and at least one variable resistor integrated in series with the eddy current coil. | 10-27-2011 |
20120092121 | BALANCED TRANSFORMER STRUCTURE - A multi-chip electronic device includes a first winding having a first port (P+) and a second port (P−). The first winding is formed in a metal layer of a first chip. The device further includes a second winding having a third (S+) and a fourth port (S−). The second winding is formed in a metal layer of a second chip. A center tap of the second winding is connected to a reference potential. | 04-19-2012 |
20120122395 | THROUGH CHIP COUPLING FOR SIGNAL TRANSPORT - Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit. | 05-17-2012 |
20130106532 | BAND-PASS FILTER USING LC RESONATORS | 05-02-2013 |
20130181534 | THROUGH-CHIP INTERFACE (TCI) STRUCTURE FOR WIRELESS CHIP-TO-CHIP COMMUNICATION - A transformer for RF and other frequency through-chip-interface (TCI) applications includes multiple chips in wireless electronic communication with one another in three-dimensional integrated circuit, 3DIC, technology. Each of the chips includes an inductor coil and a matching network that matches the impedance of the inductor coil. The matching network is electrically coupled between the inductor coil and further components and circuits formed on the chip. | 07-18-2013 |
20130207230 | ON-CHIP FERRITE BEAD INDUCTOR - A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes. | 08-15-2013 |
20130241634 | RF CALIBRATION THROUGH-CHIP INDUCTIVE COUPLING - An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils. | 09-19-2013 |
20130271223 | AMPLIFIER WITH FLOATING WELL - A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit. | 10-17-2013 |
20130328623 | LOW POWER ACTIVE FILTER - Some embodiments relate to a band-pass filter arranged in a ladder-like structure. The band-pass filter includes respective inductor-capacitor (LC) resonators arranged on respective rungs of the ladder-like structure. Respective matching circuits are arranged on a leg of the ladder-like structure between neighboring rungs. | 12-12-2013 |
20140036396 | INTEGRATED PASSIVE DEVICE FILTER WITH FULLY ON-CHIP ESD PROTECTION - The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology. | 02-06-2014 |
20140132333 | SWITCH CIRCUIT AND METHOD OF OPERATING THE SWITCH CIRCUIT - A method of electrically coupling a first node and a second node of a switch cell includes biasing the second node and a bias node of the switch cell at a direct current (DC) voltage level of a second voltage level greater than a first voltage level. A first switch unit coupled between the first node and the second node is tuned on by a first control signal having a third voltage level. The third voltage level being greater than the first voltage level, and a difference between the third voltage level and the first voltage level is about twice a difference between the second voltage level and the first voltage level. Also, a second switch unit coupled between the second node and the bias node is turned off by a second control signal having the first voltage level. | 05-15-2014 |
20140183660 | POWER CELL AND POWER CELL CIRCUIT FOR A POWER AMPLIFIER - A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin. | 07-03-2014 |
20140184275 | POWER CELL, POWER CELL CIRCUIT FOR A POWER AMPLIFIER AND A METHOD OF MAKING AND USING A POWER CELL - A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer. | 07-03-2014 |
20140266419 | VOLTAGE CONTROLLER FOR RADIO-FREQUENCY SWITCH - One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example. | 09-18-2014 |
20140266512 | CMOS BAND-PASS FILTER - A band-pass filter is provided that is configured to output a signal with a frequency within a desired frequency range and to attenuate signals with frequencies outside the desired frequency range. The band-pass filter comprises a CMOS resonator that comprises a resonator cavity and a reflector. The band-pass filter also comprises an impedance convertor that is configured to inhibit at least some insertion losses on the band-pass filter. The band-pass filter also comprises a variable capacitor that is connected between the CMOS resonator and the impedance convertor. The desired frequency range of the band-pass filter can be tuned by adjusting the capacitance of the variable capacitor. | 09-18-2014 |
20140374881 | CONCENTRIC CAPACITOR STRUCTURE - A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates. | 12-25-2014 |
20150014786 | HIGH PERFORMANCE POWER CELL FOR RF POWER AMPLIFIER - A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell. | 01-15-2015 |
20150015336 | CMOS CASCODE POWER CELLS - A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well. | 01-15-2015 |
20150084158 | THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME - The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. | 03-26-2015 |
Patent application number | Description | Published |
20120179638 | RELATIVE VARIABLE SELECTION SYSTEM AND SELECTION METHOD THEREOF - The present invention discloses a relative variable selection system and a selection method thereof. In the present invention, the receiving module receives a plurality of variables. Based on a correlation coefficient of variables, a first selection module sequentially selects variables with a correlation coefficient greater than a first threshold value. Based on the variables selected by the first selection module, a first calculating module selects a regression value and a weighted value corresponding to the foregoing variables. Based on the weighted values, a second selection module sequentially selects variables with a weighted value smaller than a second threshold value. Based on the variables selected by the second selection module, a second calculating module calculates analyzed values of the foregoing variables. Based on the analyzed values of the variables, a third selection module selects analyzed values which are greater than the target value. | 07-12-2012 |
20120179721 | Fitness Function Analysis System and Analysis Method Thereof - The present invention discloses a fitness function analysis system and an analysis method thereof. Wherein, an initializing module initiates a plurality of reference solutions. Based on fitness functions of reference solutions, a searching module searches a fitness function adjacent to the fitness functions. While an adjacent fitness function close to the fitness function is greater than the fitness function, the searching module replaces the fitness function by the adjacent fitness function. A calculating module calculates the proportion of any fitness function to the summation of the fitness functions. While the searching module counts the number of times that the searching module has searched an adjacent function close to the fitness function, the number of times exceeds a threshold value, and there is no adjacent fitness function greater than the fitness function, a processing module will generate another fitness function corresponding to the fitness function and compare the two fitness functions. | 07-12-2012 |
20150049619 | EVALUATING THE RELIABILITY OF DETERIORATION-EFFECT MULTI-STATE FLOW NETWORK SYSTEM AND METHOD THEREOF` - A system of evaluating the reliability of deterioration-effect multi-state flow network and method thereof are disclosed in present invention. The system can evaluate the probability that d units of data of flow can be transmitted from a source node to a sink node. In practical application, the flow in a deterioration-effect multi-state flow network may undergo a loss due to deterioration. For example, electrical power will decrease if the transmission distance is too great. Therefore, how to evaluate the reliability of deterioration-effect multi-state flow network becomes an important issue. | 02-19-2015 |
20150052232 | RELIABILITY OF MULTI-STATE INFORMATION NETWORK EVALUATION METHOD AND SYSTEM THEREOF - A reliability of multi-state information network evaluation method and system thereof are disclosed in the present invention. The system comprises a storage unit, a universal generation function process unit, a reliability calculating unit, and a judging unit. The feature of the invention is to develop a novel method for evaluation of the reliability based on the disconnectedness between nodes and targets. Therefore, a decision-maker can analyze the network according to the invention and apply the analysis result in lots of applications, such as computer communication system, electronic transmission system, transportation system, etc. | 02-19-2015 |