Patent application number | Description | Published |
20090195310 | LNA HAVING A POST-DISTORTION MODE AND A HIGH-GAIN MODE - A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor, a second transistor, a third transistor and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third and fourth transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third and fourth transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors, resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA. | 08-06-2009 |
20100029223 | METHODS AND APPARATUS FOR IMPLEMENTING PHASE ROTATION AT BASEBAND FREQUENCY FOR TRANSMIT DIVERSITY - An apparatus for implementing phase rotation at baseband frequency for transmit diversity may include a primary transmit signal path and a diversity transmit signal path. Both the primary transmit signal path and the diversity transmit signal path may receive a primary transmit signal. A signal selector within the diversity transmit signal path may perform phase rotation with respect to the primary transmit signal while the primary transmit signal is at a baseband frequency, thereby producing a diversity transmit signal. | 02-04-2010 |
20100029323 | SYSTEMS AND METHODS FOR ADJUSTING THE GAIN OF A RECEIVER THROUGH A GAIN TUNING NETWORK - A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network. | 02-04-2010 |
20100289537 | SYSTEMS AND METHODS FOR PRODUCING A PREDETERMINED OUTPUT IN A SEQUENTIAL CIRCUIT DURING POWER ON - An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage. | 11-18-2010 |
20100328127 | INTERFERENCE REDUCTION USING VARIABLE DIGITAL-TO-ANALOG CONVERTER (DAC) SAMPLING RATES - A method for interference reduction is described. A sampling frequency is selected for a digital-to-analog converter (DAC) so that images within a DAC output signal do not interfere with one or more receivers. A sample rate is adjusted of an input signal that is provided to the DAC to match the sampling frequency for the DAC. | 12-30-2010 |
20110105070 | Direct conversion receiver architecture - A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. | 05-05-2011 |
20130242800 | CLASSIFIER FOR RADIO FREQUENCY FRONT-END (RFFE) DEVICES - A method for classifying radio frequency front-end (RFFE) devices. The method includes enumerating a radio frequency front-end (RFFE) slave device according to at least one classifier bit within the RFFE slave device. The method also includes adjusting an RFFE control interface of an RFFE master device according to slave device configuration information determined from the at least one classifier bit within the RFFE slave device. | 09-19-2013 |
20140254448 | METHOD AND APPARATUS FOR FACILITATING POWER CONSERVATION VIA TIME-GATING IN A WIRELESS COMMUNICATION SYSTEM - The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal. | 09-11-2014 |
Patent application number | Description | Published |
20130122833 | RADIO FREQUENCY PACKAGE ON PACKAGE CIRCUIT - A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package. The first radio frequency package includes radio frequency components. The radio frequency package on package (PoP) circuit also includes a second radio frequency package. The second radio frequency package includes radio frequency components. The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance. | 05-16-2013 |
20130225107 | WIRELESS DEVICE WITH FILTERS TO SUPPORT CO-EXISTENCE IN ADJACENT FREQUENCY BANDS - Techniques for using a narrow filter located before a power amplifier to reduce interference in an adjacent frequency band are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes the narrow filter and the power amplifier. The narrow filter is for a first frequency band (e.g., Band 40) and has a first bandwidth that is more narrow than the first frequency band. The narrow filter receives and filters an input radio frequency (RF) signal and provides a filtered RF signal. The power amplifier receives and amplifies the filtered RF signal and provides an amplified RF signal. The apparatus may further include a full filter for the first frequency band and located after the power amplifier. The full filter receives and filters the amplified RF signal and provides an output RF signal when it is selected for use. | 08-29-2013 |
20130231064 | SINGLE-CHIP SIGNAL SPLITTING CARRIER AGGREGATION RECEIVER ARCHITECTURE - A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path. | 09-05-2013 |
20140003300 | ANTENNA INTERFACE CIRCUITS FOR CARRIER AGGREGATION ON MULTIPLE ANTENNAS | 01-02-2014 |
20140072001 | CARRIER AGGREGATION RECEIVER ARCHITECTURE - A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module. | 03-13-2014 |
20140213209 | SINGLE-INPUT MULTIPLE-OUTPUT AMPLIFIERS WITH INDEPENDENT GAIN CONTROL PER OUTPUT - Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first and second amplifier circuits. The first amplifier circuit may receive and amplify an input radio frequency (RF) signal based on a first variable gain and provide a first amplified RF signal. The second amplifier circuit may receive and amplify the input RF signal based on a second variable gain and provide a second amplified RF signal. The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device. | 07-31-2014 |
Patent application number | Description | Published |
20100132487 | PIPETTING DEVICE, MODULAR PIPETTING UNIT, PIPETTING SYSTEM AND METHOD FOR PIPETTING OF FLUID SAMPLES - A pipetting device having a modular pipetting unit including a pipetting tip for pipetting of fluid samples and a pump conduit for transferring a negative or positive pressure to the pipetting tip is disclosed. The pipetting tip and a portion of the pump conduit adjoining the pipetting tip mutually define a fluid sample conduit for receiving the fluid samples. The modular pipetting unit is detachably attached to an automated positioning device for positioning the modular pipetting unit. A system and method for pipetting of fluid samples using such a pipetting device are also disclosed wherein pipetting of the fluid samples is performed in such a manner that each pipetted fluid sample volume is smaller than a volume of the fluid sample conduit. | 06-03-2010 |
20110030803 | Sample Preparation Dosing Unit - A sample preparation dosing unit for liquid dosing is provided comprising an inlet port and an outlet port fluidically coupling the sample preparation dosing unit to a supply and target, respectively; a pump, fluidically arranged between the inlet port and the outlet port; an outlet flow restrictor with an outlet flow resistance, fluidically arranged between a pump outlet and outlet port; and a control arrangement with a branch, a control valve, and a control flow restrictor with a control flow resistance. The branch divides the flow at the pump outlet into an outlet flow through the outlet flow restrictor and into a control flow through the control flow restrictor. The control flow downstream of the control flow restrictor is fed, depending on the state of the control valve, either into the outlet port thereby merging with the outlet flow downstream of the outlet flow restrictor, or into a bypass conduit. | 02-10-2011 |
20130256205 | Apparatus for Separating Magnetic Particles from Liquids Containing said Particles, and an Array of Vessels Suitable for use with such an Apparatus - An apparatus for separating magnetic particles from a liquid which contains said particles, said liquid being contained in an elongated vessel ( | 10-03-2013 |
20150056111 | PIPETTING DEVICE, MODULAR PIPETTING UNIT, PIPETTING SYSTEM AND METHOD FOR PIPETTING OF FLUID SAMPLES - A pipetting device having a modular pipetting unit including a pipetting tip for pipetting of fluid samples and a pump conduit for transferring a negative or positive pressure to the pipetting tip is disclosed. The pipetting tip and a portion of the pump conduit adjoining the pipetting tip mutually define a fluid sample conduit for receiving the fluid samples. The modular pipetting unit is detachably attached to an automated positioning device for positioning the modular pipetting unit. A system and method for pipetting of fluid samples using such a pipetting device are also disclosed wherein pipetting of the fluid samples is performed in such a manner that each pipetted fluid sample volume is smaller than a volume of the fluid sample conduit. | 02-26-2015 |