Patent application number | Description | Published |
20080206960 | REWORKABLE CHIP STACK - A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point. | 08-28-2008 |
20090072392 | Techniques For Forming Solder Bump Interconnects - Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer. | 03-19-2009 |
20090085202 | Methods and Apparatus for Assembling Integrated Circuit Device Utilizing a Thin Si Interposer - Methods of assembling an integrated circuit are provided. An interposer supported by an integrated handler is solder bumped onto one or more bond pads on a substrate. The integrated handler is removed from the interposer. A side of the interposer opposite that of the substrate is solder bumped to one or more bond pads on a chip. | 04-02-2009 |
20090311849 | METHODS OF SEPARATING INTEGRATED CIRCUIT CHIPS FABRICATED ON A WAFER - Improved methods of separating integrated circuit chips fabricated on a single wafer are provided. In an embodiment, a method of separating integrated circuit chips fabricated on a wafer comprises: attaching a support to a back surface of the wafer; dicing the wafer to form individual integrated circuit chips attached to the support; attaching a carrier comprising a releasable adhesive material to a front surface of the wafer opposite from the back surface; separating the support from the back surface of the wafer; subjecting the carrier to an effective amount of heat, radiation, or both to reduce the adhesiveness of the adhesive material to allow for removal of at least one of the integrated circuit chips from the carrier; and picking up and moving at least one of the integrated circuit chips using a tool configured to handle the integrated circuit chips. | 12-17-2009 |
20100326702 | INTEGRATED CIRCUIT ASSEMBLY - Methods and apparatus for forming an integrated circuit assembly are presented, for example, three dimensional integrated circuit assemblies. Lower height 3DIC assemblies due Use of, for example, thinned wafers, low-height solder bumps, and through silicon vias provide for low height three dimensional integrated circuit assemblies. For example, a method for forming an integrated circuit assembly comprises forming first solder bumps on a first die, and forming a first structure comprising the first die, the first solder bumps, a first flux, and a first substratum. The first die is placed upon the first substratum. The first solder bumps are between the first die and the first substratum. The first flux holds the first die substantially flat and onto the first substratum. | 12-30-2010 |
20110290402 | Handler Attachment for Integrated Circuit Fabrication - A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive. | 12-01-2011 |
20110290406 | Laser Ablation for Integrated Circuit Fabrication - A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler. | 12-01-2011 |
20110290413 | Laser Ablation of Adhesive for Integrated Circuit Fabrication - A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. | 12-01-2011 |
20120138769 | Techniques for Forming Solder Bump Interconnects - Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer. | 06-07-2012 |
20120267729 | SELF-SEALED FLUIDIC CHANNELS FOR NANOPORE ARRAY - A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore. | 10-25-2012 |
20120279287 | Transferable Probe Tips - Transferable probe tips including a metallic probe, a delamination layer covering a portion of the metallic probe, and a bonding alloy, wherein the bonding alloy contacts the metallic probe at a portion of the probe that is not covered by the delamination layer are provided herein. Also, techniques for creating a transferable probe tip are provided, including etching a handler substrate to form one or more via arrays, depositing a delamination layer in each via array, depositing one or more metals in each via array to form a probe tip structure, and depositing a bonding alloy on a portion of the probe tip structure that is not covered by the delamination layer. Additionally, techniques for transferring transferable probe tips are provided, including removing a handler substrate from a probe tip structure, and transferring the probe tip structure via flip-chip joining the probe tip structure to a target probe head substrate. | 11-08-2012 |
20120326247 | SELF-SEALED FLUIDIC CHANNELS FOR A NANOPORE ARRAY - A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore. | 12-27-2012 |
20130015440 | INTEGRATED CIRCUIT (IC) TEST PROBEAANM Dang; BingAACI ChappaquaAAST NYAACO USAAGP Dang; Bing Chappaqua NY USAANM Knickerbocker; John U.AACI MonroeAAST NYAACO USAAGP Knickerbocker; John U. Monroe NY USAANM Liu; YangAACI OSSININGAAST NYAACO USAAGP Liu; Yang OSSINING NY US - A test probe head for probing integrated circuit (IC) chips and method of making test heads. The test head includes an array of vias (e.g., annular vias or grouped rectangular vias) through, and exiting one surface of, a semiconductor layer, e.g., a silicon layer. The vias, individual test probe tips, may be on a pitch at or less than fifty microns (50 μm). The probe tips may be stiffened with SiO | 01-17-2013 |
20130283584 | Assembly of Electronic and Optical Devices - An assembly tool apparatus includes a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, a jig having an assembly surface operative to move from a first orientation relative to the axis to a second orientation relative to the axis, a first tool tip operative to engage with and be positioned by the manipulator, and a second tool tip operative to engage with and be positioned by the manipulator. | 10-31-2013 |
20130283591 | Assembly of Electronic and Optical Devices - A method for operating an assembly tool includes deposing a first component on an assembly surface with a first tool tip of a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, deposing a second component on the assembly surface, changing an orientation of the assembly surface relative to the axis from a first orientation to a second orientation, lifting the first component from the assembly surface with a second tool tip of the manipulator, and deposing the first component on the second component. | 10-31-2013 |
20130327811 | THREE DIMENSIONAL FLIP CHIP SYSTEM AND METHOD - Solder is simultaneously transferred from a mold to a plurality of 3D assembled modules to provide solder bumps on the modules. The mold includes cavities containing injected molten solder or preformed solder balls. A fixture including resilient pressure pads and vacuum lines extending through the pads applies pressure to the modules when they are positioned on the mold. Following reflow and solder transfer to the modules, the fixture is displaced with respect to the mold. The modules, being attached to the fixture by vacuum pressure through the pads, are displaced from the mold with the fixture. | 12-12-2013 |
20130330880 | THREE DIMENSIONAL FLIP CHIP SYSTEM AND METHOD - Solder is simultaneously transferred from a mold to a plurality of 3D assembled modules to provide solder bumps on the modules. The mold includes cavities containing injected molten solder or preformed solder balls. A fixture including resilient pressure pads and vacuum lines extending through the pads applies pressure to the modules when they are positioned on the mold. Following reflow and solder transfer to the modules, the fixture is displaced with respect to the mold. The modules, being attached to the fixture by vacuum pressure through the pads, are displaced from the mold with the fixture. | 12-12-2013 |
20140069817 | DIRECT INJECTION MOLDED SOLDER PROCESS FOR FORMING SOLDER BUMPS ON WAFERS - Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers. | 03-13-2014 |
20140144593 | WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION - Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers that absorb long-wavelength infrared radiation to achieve wafer debonding by infrared radiation ablation. | 05-29-2014 |
20140145884 | PACKAGE STRUCTURES TO IMPROVE ON-CHIP ANTENNA PERFORMANCE - A radio frequency integrated circuit (RFIC) chip package is provided having an RFIC chip and an integrated antenna structure. The integrated antenna structure includes an on-chip antenna having one or more radiator elements formed as part of a back-end-of-line structure of the RFIC chip. The antenna structure further includes a superstrate structure disposed on the back-end-of-line structure of the RFIC chip. The superstrate structure includes at least one substrate layer and a focusing metal element. The focusing metal element has a structure that is complementary to the on-chip radiator elements and which is configured to focus electromagnetic radiation to and from the planar antenna structure. The superstrate structure improves the performance (e.g., antenna gain and bandwidth) of the on-chip antennas for millimeter-wave applications. | 05-29-2014 |
20140147986 | WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION - Methods are provided for handling a device wafer. For example, a method includes providing a stack structure having a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and handler wafer, and irradiating the bonding structure with long-wavelength infrared energy to ablate the bonding structure. | 05-29-2014 |
20140201971 | ASSEMBLY OF ELECTRONIC AND OPTICAL DEVICES - A method for operating an assembly tool includes deposing a first component on an assembly surface with a first tool tip of a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, deposing a second component on the assembly surface, changing an orientation of the assembly surface relative to the axis from a first orientation to a second orientation, lifting the first component from the assembly surface with a second tool tip of the manipulator, and deposing the first component on the second component. | 07-24-2014 |
20150035173 | ADHESIVES FOR BONDING HANDLER WAFERS TO DEVICE WAFERS AND ENABLING MID-WAVELENGTH INFRARED LASER ABLATION RELEASE - Methods are provided to form adhesive materials that are used to temporarily bond handler wafers to device wafers, and which enable mid-wavelength infrared laser ablation release techniques to release handler wafers from device wafers. | 02-05-2015 |
20150035554 | WAFER DEBONDING USING MID-WAVELENGTH INFRARED RADIATION ABLATION - Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers which are laser-ablatable using mid-wavelength infrared radiation | 02-05-2015 |
20150132924 | HANDLER WAFER REMOVAL - A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer. | 05-14-2015 |
20150241476 | METHOD OF FORMING SURFACE PROTRUSIONS ON AN ARTICLE AND THE ARTICLE WITH THE PROTRUSIONS ATTACHED - A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure. | 08-27-2015 |
20150287960 | THIN, FLEXIBLE MICROSYSTEM WITH INTEGRATED ENERGY SOURCE - A system comprising a first dielectric element and a second dielectric element each having a first surface, wherein the first surface of the first dielectric element and the first surface of the second dielectric element are joined. The system further comprises one or more enclosed voids within the joined first and second dielectric elements. The system further comprises a flexible battery in a first enclosed void of the one or more enclosed voids, the flexible battery having a thickness of less than about 150 microns. | 10-08-2015 |
20150318210 | METHOD AND APPARATUS FOR LASER DICING OF WAFERS - A method includes cutting a semiconductor wafer on a substrate wafer using at least one laser. By setting the laser to a set of parameters that define a laser beam, the laser beam can avoid ablation of the substrate wafer. The laser beam is also set equal to, or within, an ablation threshold of the semiconductor wafer for selectively ablating the semiconductor wafer. The set of parameters includes wavelength, pulse width and pulse frequency. | 11-05-2015 |
20150340765 | INTEGRATION OF AREA EFFICIENT ANTENNAS FOR PHASED ARRAY OR WAFER SCALE ARRAY ANTENNA APPLICATIONS - Package structures are provided for integrally packaging antennas with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an RFIC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material. | 11-26-2015 |
20160049344 | Wafer Level Overmold for Three Dimensional Surfaces - Embodiments of the invention include a method for shaping a flexible integrated circuit to a curvature and the resulting structure. A flexible circuit is provided. An epoxy resin and amine composition is deposited on the flexible integrated circuit. The deposited epoxy resin and amine composition is B-staged. The flexible integrated circuit is placed within a mold of a curvature. The B-staged epoxy resin and amine composition is cured subsequent to placing the flexible integrated circuit within the mold of the curvature. | 02-18-2016 |
20160074323 | MICROCHIP SUBSTANCE DELIVERY DEVICES HAVING LOW-POWER ELECTROMECHANICAL RELEASE MECHANISMS - Electromechanical substance delivery devices are provided which implement low-power electromechanical release mechanisms for controlled delivery of substances such as drugs and medication. For example, an electromechanical device includes a substrate having a cavity formed in a surface of the substrate, a membrane disposed on the surface of the substrate covering an opening of the cavity, and a seal disposed between the membrane and the surface of the substrate. The seal surrounds the opening of the cavity, and the seal and membrane are configured to enclose the cavity and retain a substance within the cavity. An electrode structure is configured to locally heat a portion of the membrane in response to a control voltage applied to the electrode structure, and create a stress that causes a rupture in the locally heated portion of the membrane to release the substance from within the cavity. | 03-17-2016 |
20160084876 | TEST PROBE SUBSTRATE - A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques. | 03-24-2016 |
20160084882 | TEST PROBE HEAD FOR FULL WAFER TESTING - A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 μm). The subarray probe tips may be on a pitch at or less than fifty microns (50 μm). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing. | 03-24-2016 |
20160111387 | PLANARITY-TOLERANT REWORKABLE INTERCONNECT WITH INTEGRATED TESTING - A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint. | 04-21-2016 |
20160113119 | SUBSTRATE VIA FILLING - A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate. | 04-21-2016 |
20160118358 | DIRECT INJECTION MOLDED SOLDER PROCESS FOR FORMING SOLDER BUMPS ON WAFERS - Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers. | 04-28-2016 |