Patent application number | Description | Published |
20090068812 | Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 03-12-2009 |
20110013463 | Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 01-20-2011 |
20120132979 | Memory Devices And Methods Of Forming Memory Devices - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 05-31-2012 |
20130193505 | Memory Devices and Methods of Forming Memory Devices - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 08-01-2013 |
20140035021 | Memory Devices Comprising Word Line Structures, At Least One Select Gate Structure, and a Plurality Of Doped Regions - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 02-06-2014 |
Patent application number | Description | Published |
20090186037 | METHODS FOR INHIBITING AN IMMUNE RESPONSE BY BLOCKING THE GP39/CD40 AND CTLA4/CD28/B7 PATHWAYS AND COMPOSITIONS FOR USE THEREWITH - The present invention provides a method for inhibiting an immune response and a method for inhibiting rejection of transplanted tissues. This method comprises preventing an endogenous molecule on a cell selected from the group consisting of gp39 and CD40 antigens from binding its endogenous ligand and preventing an endogenous molecule on a cell selected from the group consisting of CTLA4, CD28, and B7 antigens from binding its endogenous ligand. The prevention of such molecules from binding their ligand thereby blocks two independent signal pathways and inhibits the immune response resulting in transplanted tissue rejection. | 07-23-2009 |
20110129496 | Use of mTOR Inhibitors to Enhance T Cell Immune Responses - It is disclosed herein that treatment of a subject with an mTOR inhibitor enhances antigen-specific T cell immune responses. Thus, provided herein is a method of enhancing an antigen-specific T cell response in a subject by administering to the subject a therapeutically effective amount of an mTOR inhibitor. The antigen can be any antigen, such as an antigen from a pathogen or a vaccine, or a tumor antigen. In some embodiments, the method further comprises administering to the subject a vaccine, such as a virus vaccine or a cancer vaccine. The mTOR inhibitor can be administered either before or after vaccination to enhance the quantity and quality of the T cell immune response and immunological memory. In some examples, the mTOR inhibitor is rapamycin or a rapamycin analog. | 06-02-2011 |
20140093497 | ANTI-CD40 ANTIBODIES AND USES THEREOF - The present invention relates to antibodies specific for a particular epitope on CD40 and antibodies that bind CD40 and have particular functional characteristics. The present invention also relates to fragments of these antibodies, uses of the antibodies for reduction or treatment of transplant rejection and graft-versus-host disease, and methods for making the antibodies. | 04-03-2014 |
20140370059 | USE OF mTOR INHIBITORS TO ENHANCE T CELL IMMUNE RESPONSES - It is disclosed herein that treatment of a subject with an mTOR inhibitor enhances antigen-specific T cell immune responses. Thus, provided herein is a method of enhancing an antigen-specific T cell response in a subject by administering to the subject a therapeutically effective amount of an mTOR inhibitor. The antigen can be any antigen, such as an antigen from a pathogen or a vaccine, or a tumor antigen. In some embodiments, the method further comprises administering to the subject a vaccine, such as a virus vaccine or a cancer vaccine. The mTOR inhibitor can be administered either before or after vaccination to enhance the quantity and quality of the T cell immune response and immunological memory. In some examples, the mTOR inhibitor is rapamycin or a rapamycin analog. | 12-18-2014 |
Patent application number | Description | Published |
20120172927 | LEFT ATRIAL APPENDAGE OCCLUSIVE DEVICES - An occlusive device for left atrial appendage occlusion that has a membrane component configured to inhibit passage of blood and an expandable frame formed from a plurality of wires having a cupped occlusive component at least partially covered with the membrane component, one or more anchors with looped ends and a hub component. The occlusive device can be delivered percutaneously. The occlusive device is useful in the occlusion of the left atrial appendage. | 07-05-2012 |
20130165967 | HEART OCCLUSION DEVICES - This disclosure is directed to an aperture occlusion device and a method for occluding an aperture, including a perimembranous ventricular septal defect. The aperture occlusion device includes a wire frame element. The wire frame forms geometric shapes that include an occluder region and a securing region. The occluder region and the securing region are separated by an attachment region including a waist. The occluder region and securing region can include membranous coverings. The device can be attached to a delivery hub. The wires forming the occluder region and securing region can have a shape-memory capability such that they can be collapsed and distorted in a sheath during delivery, but resume and maintain their intended shape after delivery. | 06-27-2013 |
20130245666 | OCCLUSIVE DEVICES - An occlusive device includes a frame element having a distal end and a proximal end, and a delivery configuration and a deployed configuration. The occlusive device also includes an occlusive face having a peripheral edge, where the occlusive face positioned toward the proximal end of the frame element. The occlusive device also includes at least one anchor positioned at the peripheral edge of the occlusive face, where the at least one anchor extends at an acute angle to the peripheral edge of the occlusive face. | 09-19-2013 |
20140142610 | Space Filling Devices - A device includes a plurality of elongate members, an occlusive component, and a support component. The occlusive component includes a plurality of first features each defined by a first portion of a respective elongate member. The support component includes a plurality of second features each defined by a second portion of the respective elongate member. A first termination element is defined by proximal end portions of the plurality of elongate members and located near a proximal end of the device, and a second termination element is defined by distal end portions of the plurality of elongate members and located near a distal end of the device. One or more anchor elements include a frame attachment portion and an anchor portion, the frame attachment portion including a first portion of a fixation elongate element wrapped around an elongate member, and the anchor portion including an anchor feature. | 05-22-2014 |
20140142617 | JOINT ASSEMBLY FOR MEDICAL DEVICES - A device for occluding an aperture in a body of a patient includes a frame that includes a plurality of elongate members and a hub component that includes a plurality of attachment members, wherein for each elongate member of the plurality of elongate members a first end of the elongate member is fixedly attached to an attachment member of the plurality of attachment members at an attachment region. The frame and the hub component together form at least one occlusive element. Each receptacle of the plurality of attachment members is configured to pivot with respect to the hub component, such that each attachment region is movable with respect to the hub component. | 05-22-2014 |
20140379019 | OCCLUSIVE DEVICES - An occlusive device includes a frame element having a distal end and a proximal end, and a delivery configuration and a deployed configuration. The occlusive device also includes an occlusive face having a peripheral edge, where the occlusive face positioned toward the proximal end of the frame element. The occlusive device also includes at least one anchor positioned at the peripheral edge of the occlusive face, where the at least one anchor extends at an acute angle to the peripheral edge of the occlusive face. | 12-25-2014 |
20140379020 | LEFT ATRIAL APPENDAGE OCCLUSIVE DEVICES - An occlusive device for left atrial appendage occlusion that has a membrane component configured to inhibit passage of blood and an expandable frame formed from a plurality of wires having a cupped occlusive component at least partially covered with the membrane component, one or more anchors with looped ends and a hub component. The occlusive device can be delivered percutaneously. The occlusive device is useful in the occlusion of the left atrial appendage. | 12-25-2014 |
Patent application number | Description | Published |
20120181936 | SYSTEM AND METHOD FOR METERED DOSAGE ILLUMINATION IN A BIOANALYSIS OR OTHER SYSTEM - A system and method for metered dosage illumination in a bioanalysis or other system. In accordance with an embodiment, an illumination system or subsystem is described that can provide optimized amounts of excitation light within the short exposure times necessary to measure fast biological activity. The amount of light can be precisely measured to provide quantitative results. The light flux can also be precisely controlled to generate only a prescribed minimum amount of light, in order to reduce adverse lighting effects on both fluors and samples. Although the examples herein illustrate the providing of metered dosage illumination in the context of a bioanalysis system, the techniques can be similarly used to provide metered dosage illumination in the context of other types of system. | 07-19-2012 |
20120181937 | SYSTEM AND METHOD FOR METERED DOSAGE ILLUMINATION IN A BIOANALYSIS OR OTHER SYSTEM - A system and method for metered dosage illumination in a bioanalysis or other system includes an illumination system or subsystem that can provide optimized amounts of excitation light within the short exposure times necessary to measure fast biological activity. The amount of light can be precisely measured to provide quantitative results. The light flux can be precisely controlled to generate a prescribed minimum amount of light, in order to reduce adverse lighting effects on both fluors and samples. The system and method is particularly useful in any quality-control, analysis, or assessment-based environment. Typical research and development applications can include quality control, instrument calibration, and light output standardization; while clinical and diagnostics applications can include clinical monitoring, bioassay calibration and control for diagnostics, treatment and or therapeutic evaluation. | 07-19-2012 |
20130234047 | SYSTEM AND METHOD FOR CONTROLLED INTENSITY ILLUMINATION IN A BIOANALYSIS OR OTHER SYSTEM - A system and method for controlled illumination in a bioanalysis or other system where excitation of fluorescent molecules is desirable. In an embodiment, an illumination system is described which can provide excitation light at a controlled intensity to provide quantitative results. In an embodiment, a solid state light engine is described which includes a plurality of color channels each providing light output suitable for exciting a fluorescent molecule, a light to frequency converter which receives a portion of the light output, a counter which maintains a count of a signal from the light to frequency converter, and a light intensity circuit, responsive to the counter, which adjusts the color channels to control the intensity of the light output. | 09-12-2013 |
Patent application number | Description | Published |
20090203053 | METHODS AND MATERIALS FOR AMPLIFICATION OF A SIGNAL IN AN IMMUNOASSAY - Ultrafine particles are provided having a core region that has a signal amplifying molecule and a shell region that surrounds the core region. The shell region has at least one antibody affixed to its surface that is specific for at least one antigen. Alternatively, the ultrafine particles may entrap the signal amplifying molecule within its matrix and may also have antibodies affixed to its surface for molecular recognition. Ultrafine particles are also provided having a matrix component that includes a signal amplifying molecule and at least one antibody specific for the antigen or biomaterial. The ultrafine particles of the present disclosure may be used in assays for the detection, including quantification, of one or more antigens present in a biological sample. | 08-13-2009 |
20130017148 | SYSTEMS FOR PRODUCING MULTILAYERED PARTICLES, FIBERS AND SPRAYS AND METHODS FOR ADMINISTERING THE SAME - Capsules and particles with at least one encapsulated and/or entrapped agent, such as therapeutic agent, imaging agents, and other constituents may be produced by electrohydrodynamic processes. More particularly, the agent encapsulated in a vehicle, capsule, particle, vector, or carrier may maximize treatment and/or imaging of malignant cancers while minimizing the adverse effects of treatment and/or imaging. | 01-17-2013 |
20130224774 | METHODS AND MATERIALS FOR AMPLIFICATION OF A SIGNAL IN AN IMMUNOASSAY - Ultrafine particles are provided having a core region that has a signal amplifying molecule and a shell region that surrounds the core region. The shell region has at least one antibody affixed to its surface that is specific for at least one antigen. Alternatively, the ultrafine particles may entrap the signal amplifying molecule within its matrix and may also have antibodies affixed to its surface for molecular recognition. Ultrafine particles are also provided having a matrix component that includes a signal amplifying molecule and at least one antibody specific for the antigen or biomaterial. The ultrafine particles of the present disclosure may be used in assays for the detection, including quantification, of one or more antigens present in a biological sample. | 08-29-2013 |
Patent application number | Description | Published |
20110066529 | NEGOTIABLE INSTRUMENT ELECTRONIC CLEARANCE MONITORING SYSTEMS AND METHODS - Methods, devices, and systems for analyzing negotiated negotiable instruments are described. A computer system, including a computer readable storage device and a processor may be provided. A plurality of electronic files may be received. Each of these electronic files of the plurality of electronic files may include an electronic image of at least a portion of a negotiable instrument and include a plurality of data fields. The plurality of electronic files may be divided into subsets based on whether data is available in particular data fields of the electronic files. Based upon the subset an electronic file is made a member of, various selection criteria may be applied to determine if the electronic file is a candidate for suspicious and/or illegal activity. Statistics may be calculated about the analysis process to determine the quality and effectiveness of various analysis methods. | 03-17-2011 |
20110066564 | NEGOTIABLE INSTRUMENT ELECTRONIC CLEARANCE SYSTEMS AND METHODS - Methods, devices, and systems for analyzing negotiated negotiable instruments for unlawful activity are described. A computer system, including a computer readable storage device and a processor may be provided. A plurality of electronic files may be received. Each of these electronic files of the plurality of electronic files may include an electronic image of at least a portion of a negotiable instrument and include a plurality of data fields. The plurality of electronic files may be divided into subsets based on whether data is available in particular data fields of the electronic files. Based upon the subset an electronic file is made a member of, various selection criteria may be applied to determine if the electronic file is a candidate for suspicious and/or illegal activity. Also, a listing of candidates for suspicious and/or illegal activity may be presented to a user. | 03-17-2011 |
20120158727 | NEGOTIABLE INSTRUMENT ELECTRONIC CLEARANCE SYSTEMS AND METHODS - Methods, devices, and systems for analyzing negotiated negotiable instruments for unlawful activity are described. A computer system, including a computer readable storage device and a processor may be provided. A plurality of electronic files may be received. Each of these electronic files of the plurality of electronic files may include an electronic image of at least a portion of a negotiable instrument and include a plurality of data fields. The plurality of electronic files may be divided into subsets based on whether data is available in particular data fields of the electronic files. Based upon the subset an electronic file is made a member of, various selection criteria may be applied to determine if the electronic file is a candidate for suspicious and/or illegal activity. Also, a listing of candidates for suspicious and/or illegal activity may be presented to a user. | 06-21-2012 |
20130179317 | NEGOTIABLE INSTRUMENT ELECTRONIC CLEARANCE MONITORING SYSTEMS AND METHODS - Methods, devices, and systems for analyzing negotiated negotiable instruments are described. A computer system, including a computer readable storage device and a processor may be provided. A plurality of electronic files may be received. Each of these electronic files of the plurality of electronic files may include an electronic image of at least a portion of a negotiable instrument and include a plurality of data fields. The plurality of electronic files may be divided into subsets based on whether data is available in particular data fields of the electronic files. Based upon the subset an electronic file is made a member of, various selection criteria may be applied to determine if the electronic file is a candidate for suspicious and/or illegal activity. Statistics may be calculated about the analysis process to determine the quality and effectiveness of various analysis methods. | 07-11-2013 |
Patent application number | Description | Published |
20120236201 | DIGITAL ASSET MANAGEMENT, AUTHORING, AND PRESENTATION TECHNIQUES - Various techniques are disclosed for authoring and/or presenting packages of multimedia content. In at least one embodiment, the digital multimedia package may include video content, audio content, and text transcription content representing a transcription of the audio content. The video content, audio content, and text transcription content are each maintained in continuous synchronization with each other during video playback, and also as a user selectively navigates to different scenes of the video content. The text transcription content is presented via an interactive Resources Display GUI. Interacting with the Resources Display GUI, a user may cause the displayed text to dynamically scroll to a different portion of the text transcription corresponding to a different scene of the video. In response, the concurrent presentation of video content may automatically and dynamically change to display video content corresponding to the scene associated with the text transcription currently displayed in the Resources Display GUI. | 09-20-2012 |
20140310746 | DIGITAL ASSET MANAGEMENT, AUTHORING, AND PRESENTATION TECHNIQUES - Various techniques are disclosed for authoring and/or presenting packages of multimedia content. In at least one embodiment, the digital multimedia package may include video content, audio content, and text transcription content representing a transcription of the audio content. The video content, audio content, and text transcription content are each maintained in continuous synchronization with each other during video playback, and also as a user selectively navigates to different scenes of the video content. The text transcription content is presented via an interactive Resources Display GUI. Interacting with the Resources Display GUI, a user may cause the displayed text to dynamically scroll to a different portion of the text transcription corresponding to a different scene of the video. In response, the concurrent presentation of video content may automatically and dynamically change to display video content corresponding to the scene associated with the text transcription currently displayed in the Resources Display GUI. | 10-16-2014 |
Patent application number | Description | Published |
20100191653 | PORTABLE HANDHELD DEVICE FOR WIRELESS ORDER ENTRY AND REAL TIME PAYMENT AUTHORIZATION AND RELATED METHODS - A portable handheld device for wireless order entry and real time payment authorization may include a portable housing, a display carried by the housing, an order entry input device carried by the housing, a transaction card input device carried by the housing for reading user sensitive information from a transaction card, a wireless transceiver carried by the housing, and a processor carried by the housing and connected to the display, order entry input device, transaction card input device and wireless transceiver. The processor may be for wirelessly sending input order information, and encrypting and wirelessly sending the user sensitive information from the transaction card without storing and without displaying. The processor may also be for wirelessly receiving and displaying payment authorization information based upon real time authorization from a transaction card issuing entity. | 07-29-2010 |
20120012653 | PORTABLE HANDHELD DEVICE FOR WIRELESS ORDER ENTRY AND REAL TIME PAYMENT AUTHORIZATION AND RELATED METHODS - A portable handheld device for wireless order entry and real time payment authorization may include a portable housing, a display carried by the housing, an order entry input device carried by the housing, a transaction card input device carried by the housing for reading user sensitive information from a transaction card, a wireless transceiver carried by the housing, and a processor carried by the housing and connected to the display, order entry input device, transaction card input device and wireless transceiver. The processor may be for wirelessly sending input order information, and encrypting and wirelessly sending the user sensitive information from the transaction card without storing and without displaying. The processor may also be for wirelessly receiving and displaying payment authorization information based upon real time authorization from a transaction card issuing entity. | 01-19-2012 |
20130097087 | PORTABLE HANDHELD DEVICE FOR WIRELESS ORDER ENTRY AND REAL TIME PAYMENT AUTHORIZATION AND RELATED METHODS - A portable handheld device for wireless order entry and real time payment authorization may include a portable housing, a display carried by the housing, an order entry input device carried by the housing, a transaction card input device carried by the housing for reading user sensitive information from a transaction card, a wireless transceiver carried by the housing, and a processor carried by the housing and connected to the display, order entry input device, transaction card input device and wireless transceiver. The processor may be for wirelessly sending input order information, and encrypting and wirelessly sending the user sensitive information from the transaction card without storing and without displaying. The processor may also be for wirelessly receiving and displaying payment authorization information based upon real time authorization from a transaction card issuing entity. | 04-18-2013 |
20130290192 | PORTABLE HANDHELD DEVICE FOR WIRELESS ORDER ENTRY AND REAL TIME PAYMENT AUTHORIZATION AND RELATED METHODS - A portable handheld device for wireless order entry and real time payment authorization may include a portable housing, a display carried by the housing, an order entry input device carried by the housing, a transaction card input device carried by the housing for reading user sensitive information from a transaction card, a wireless transceiver carried by the housing, and a processor carried by the housing and connected to the display, order entry input device, transaction card input device and wireless transceiver. The processor may be for wirelessly sending input order information, and encrypting and wirelessly sending the user sensitive information from the transaction card without storing and without displaying. The processor may also be for wirelessly receiving and displaying payment authorization information based upon real time authorization from a transaction card issuing entity. | 10-31-2013 |
20140172598 | PORTABLE HANDHELD DEVICE FOR WIRELESS ORDER ENTRY AND REAL TIME PAYMENT AUTHORIZATION AND RELATED METHODS - A portable handheld device for wireless order entry and real time payment authorization may include a portable housing, a display carried by the housing, an order entry input device carried by the housing, a transaction card input device carried by the housing for reading user sensitive information from a transaction card, a wireless transceiver carried by the housing, and a processor carried by the housing and connected to the display, order entry input device, transaction card input device and wireless transceiver. The processor may be for wirelessly sending input order information, and encrypting and wirelessly sending the user sensitive information from the transaction card without storing and without displaying. The processor may also be for wirelessly receiving and displaying payment authorization information based upon real time authorization from a transaction card issuing entity. | 06-19-2014 |
Patent application number | Description | Published |
20110072250 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 03-24-2011 |
20120173849 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is to required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 07-05-2012 |
20130283012 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 10-24-2013 |
20140237215 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 08-21-2014 |
Patent application number | Description | Published |
20080222333 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 09-11-2008 |
20090119489 | Methods and Apparatus for Transforming, Loading, and Executing Super-Set Instructions - Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The transformation is from an encoded assembly level format to a binary machine level format. In one technique, the transformation mechanism is invoked by a transform and load instruction that causes an instruction retrieved from program memory to be transformed into a new language format and then loaded into a transformed instruction memory. The format of the transformed instruction may be optimized to the implementation requirements, such as improving critical path timing. The transformation of instructions may extend to other needs beyond timing path improvement, for example, requiring super-set instructions for increased functionality and improvements to instruction level parallelism. Techniques for transforming, loading, and executing super-set instructions are described. | 05-07-2009 |
Patent application number | Description | Published |
20110297753 | INTEGRATED FUEL INJECTOR IGNITERS CONFIGURED TO INJECT MULTIPLE FUELS AND/OR COOLANTS AND ASSOCIATED METHODS OF USE AND MANUFACTURE - Embodiments of injectors configured for adaptively injecting multiple different fuels and coolants into a combustion chamber, and for igniting the different fuels, are disclosed herein. An injector according to one embodiment includes a body having a first end portion and a second end portion. The injector further includes a first flow channel extending through the body, and a second flow channel extending through the body that is separate from the first flow channel and electrically isolated from the first flow channel. The first flow channel is configured to receive a first fuel, and the second flow channel is configured to receive at least one of a second fuel and a coolant. The injector further comprises a valve carried by the body that is movable between a closed position and an open position to introduce at least one of the second fuel and the coolant into a combustion chamber. | 12-08-2011 |
20120037100 | METHODS AND SYSTEMS FOR ADAPTIVELY COOLING COMBUSTION CHAMBERS IN ENGINES - The present disclosure is directed to various embodiments of systems and methods for cooling a combustion chamber of an engine. One method includes introducing fuel into the combustion chamber of an engine having an energy transfer device that moves through an intake stroke, a compression stroke, a power stroke, and an exhaust stroke. The method further includes monitoring a temperature of the combustion chamber. When the temperature reaches a predetermined value, the method also includes introducing coolant into the combustion chamber only during at least one of the power stroke and the exhaust stroke of the energy transfer device. | 02-16-2012 |
20120234297 | TORQUE MULTIPLIER ENGINES - Torque multiplier engines, and associated methods and systems, are disclosed herein. An internal combustion engine in accordance with a particular embodiment can include a connecting rod operably coupling a pair of opposing pistons. The engine can further include a first bearing coupled to the connecting rod and positioned to engage a first cam groove of an inner cam drum. A second bearing coupled to the connecting rod can be positioned to engage a second cam groove on an outer cam drum. The first and second bearings can translate linear motion of the opposing pistons to rotation of the cam drums. | 09-20-2012 |
Patent application number | Description | Published |
20100245212 | MICRODISPLAY AND INTERFACE ON A SINGLE CHIP - A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same to field sequential color signals for generation of full color images. It includes column data processors having a comparator for each block of N-columns of pixels. Image data is double-buffered in SRAM memory cells located beneath the pixel electrodes, but not within each pixel. The stored data is logically associated with each pixel via the column data processors. Image compression is accomplished by converting RGB data to a variant of YUV data and sampling the color components of the converted data less frequently than the luminance components. The SRAM image buffer consumes a reduced amount of power. A temperature compensation scheme allows the temperature of the microdisplay to be sensed and the drive voltage to the pixel electrodes to be varied in response thereto. | 09-30-2010 |
20110169882 | ADJUSTMENT OF DISPLAY ILLUMINATION TIMING - A display device adjusts the operational timing of the illumination source relative to pixels of the display device. Grayscale may be generated in the pixels using pulse width modulation. The operational timing may be adjusted based on the temperature of the display device. The display device may be a liquid crystal display device and the operational timing of the illumination source may be adjusted to compensate for variation in the response time of the liquid crystal material based on temperature. | 07-14-2011 |
20110199405 | DIGITAL GRAY SCALE METHODS AND DEVICES - Methods and devices for generating grayscale using digital pulse width modulation between optical states. Grayscale may be generated for each component color using multiple algorithm cycles per display field. Subsets of binary weighted bit values for data values of each component color may be split across algorithm cycles to reduce the number of data comparisons per color per display field. The total number of data comparisons per color per display field may be reduced by half or more. | 08-18-2011 |
20110227887 | ADJUSTMENT OF LIQUID CRYSTAL DISPLAY VOLTAGE - Drive voltages of a liquid crystal display are adjusted based on one or more environmental conditions. The pixel drive voltages may be adjusted based on temperature. A pixel voltage may be varied such that it is a higher voltage at relatively lower temperatures and a lower voltage at relatively higher temperatures. The window voltage may be varied based on temperature. The window voltage may be stepped through different values within a display phase. The window voltage may be varied during a blanking period of the display phase such that the pixel sees a relatively larger voltage to obtain a desired initial state more quickly. Then, during a light modulating time period, the window voltage may be stepped such that there is a lower voltage field for holding the state of the pixel. | 09-22-2011 |
20110267362 | GAMMA VARIATION USING ILLUMINATION INTENSITY - A gamma variation of image intensity is created by varying the illumination intensity during a pulse width modulated display time period. During the pulse width modulated display time period a ramp signal may be compared with the image data to determine when pixel electrodes of the pixel array are switched. The illumination intensity may be varied in concert with ramp signal to produce a quadratic variation of displayed intensity on image data value. The illumination source could be an LED illumination source and intensity of the LED illumination source could be controlled using pulse width modulation. | 11-03-2011 |
20120069060 | NOR-BASED GRAYSCALE FOR A DIGITAL DISPLAY - A digital display provides pulse-width-modulated pixel waveforms by applying a wired-NOR function to selected bits of stored image data. Image bits are selected according to a digital sequence and the wired-NOR function results in a trigger signal that may be used to switch the state of a pixel element. The pixel element may be a pixel state latch of a pixel driver circuit. The digital display may accept conventional 24-bit color video signals (one 8-bit gray-scale value for each pixel for each of the red, green, and blue primary colors), and convert this input signal to sequential color with PWM digital gray scale drive to each pixel. | 03-22-2012 |
20120075320 | DEFECT MAPPING FOR A DIGITAL DISPLAY - A digital display with image data storage memory that minimizes the impact of defective memory cells by remapping stored image data. Memory defects may be detected by automatic or visual testing. The digital display may perform a mapping process such that image data placed in the location of the defective storage cells is based on the significance of the data, both by bit and by color. The mapping process may operate on addressed rows of memory cells of the digital display. | 03-29-2012 |
Patent application number | Description | Published |
20100028231 | SYNTHESIS AND USE OF NANOCRYSTALLINE ZEOLITES - Embodiments of the present invention relate to a method for synthesizing nanocrystalline zeolites, the method comprising contacting starting products that comprise a solvent, a silicon source, a cation base, an organic template, and an aluminum source, or any combination thereof sufficient to produce a zeolite gel by hydrolysis, heating the zeolite gel sufficient to produce a first batch of zeolite crystals and a first clear solution, separating the first batch of zeolite crystals from the first clear solution, heating the first clear solution sufficient to produce a second batch of zeolite crystals and second clear solution and separating the second batch of zeolite crystals from the second clear solution. In addition, embodiments relate to a method of using nanocrystalline zeolites, the method comprising contacting a nanocrystalline zeolite with a reductant sufficient to produce a nanocrystalline zeolite with adsorbed reductant and exposing the nanocrystalline zeolite with adsorbed reductant to reactant gases sufficient to obtain reaction products and the nanocrystalline zeolite. | 02-04-2010 |
20120027673 | SYNTHESIS OF HIERARCHICAL NANOCRYSTALLINE ZEOLITES WITH CONTROLLED PARTICLE SIZE AND MESOPOROSITY - A one step synthesis of nanocrystalline zeolites ZSM-5 and Naβ from a single template system in high yield has been discovered. The size of individual nanocrystals, as well as mesopore surface area and pore volume can be controlled by adjusting the pH of the reaction mixture, as well as the hydrothermal treatment temperature and duration. The mesopore volume and size distribution show a dependence on particle size such that smaller particles lead to higher mesopore volumes and narrower pore size distributions. | 02-02-2012 |
Patent application number | Description | Published |
20110028998 | BI-DIRECTIONAL SUTURE PASSER - A bi-directional suture passing instrument configured to approach soft tissues perpendicularly, enables safer and more efficient surgical repairs and minimally invasive techniques to be employed, useful in areas such as annulus repair, meniscal repair, shoulder arthroscopy, hernia repair, laproscopic repair, and wound closure. | 02-03-2011 |
20110270278 | ANCHOR ASSEMBLY INCLUDING EXPANDABLE ANCHOR - An anchor assembly can include at least one anchor member, such as a pair of anchor members that are configured to be implanted in a target anatomical location in a first configuration, and can subsequently be actuated to an expanded configuration that secures the anchor members in the target anatomy. The anchor assembly can further include a connector member that attaches the pair of anchor members together across a gap so as to approximate the anatomical defect. | 11-03-2011 |
20120004669 | INSERTION INSTRUMENT FOR ANCHOR ASSEMBLY - An insertion instrument is configured to eject a pair of anchor bodies across an anatomical gap so as to approximate the gap. The insertion instrument can include a single cannula that retains the pair of anchor bodies in a stacked relationship, or a pair of adjacent cannulas that each retain respective anchor bodies. The insertion instrument can be actuated so as to eject the anchor bodies into respective target anatomical locations. | 01-05-2012 |
20120143215 | INSERTION INSTRUMENT FOR ANCHOR ASSEMBLY - An insertion instrument is configured to eject at least one anchor body into respective target locations, and subsequently apply a predetermined tensile force at least one actuation member of the at least one anchor member so as to actuate the at least one anchor body from a first configuration to a second expanded configuration. The insertion instrument can include a tension assembly that applies the predetermined tensile force to the at least one actuation member. The predetermined tensile force can be defined by a distance of travel, a predetermined failure force of a fuse, or a combination of distance of travel and a predetermined failure force of a fuse. | 06-07-2012 |
Patent application number | Description | Published |
20090089454 | Network packet payload compression - Methods and apparatus relating to network packet payload compression/decompression are described. In an embodiment, an uncompressed packet payload may be compressed before being transferred between various components of a computing system. For example, a packet payload may be compressed prior to transfer between network interface cards or controllers (NICs) and storage devices (e.g., including a main system memory and/or cache(s)), as well as between processors (or processor cores) and storage devices (e.g., including main system memory and/or caches). Other embodiments are also disclosed. | 04-02-2009 |
20100042579 | GENERATING AND/OR RECEIVING, AT LEAST IN PART, AT LEAST ONE DATA ACCESS REQUEST - In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request to access at least one portion of data. The at least one request may indicate, at least in part, at least one subset of the at least one portion of the data that is of relatively higher importance than one or more other subsets of the at least one portion of the data that are of relatively lower importance. The at least one request may be to request, at least in part, that the at least one subset be accessed prior to the one or more other subsets are accessed. The at least one request may be comprised, at least in part, in at least one packet in accordance with a protocol that permits variable packet size. | 02-18-2010 |
20100131781 | Reducing network latency during low power operation - In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed. | 05-27-2010 |
20130262614 | WRITING MESSAGE TO CONTROLLER MEMORY SPACE - An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred. Many alternatives, variations, and modifications are possible. | 10-03-2013 |
Patent application number | Description | Published |
20120179853 | MEMORY ADDRESS TRANSLATION - The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address. | 07-12-2012 |
20120226887 | LOGICAL ADDRESS TRANSLATION - The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range. | 09-06-2012 |
20120311406 | DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS - Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks. | 12-06-2012 |
20130227247 | MEMORY ADDRESS TRANSLATION - The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address. | 08-29-2013 |
20130246891 | PHYSICAL PAGE, LOGICAL PAGE, AND CODEWORD CORRESPONDENCE - The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory. | 09-19-2013 |
20130342375 | DATA COMPRESSION AND MANAGEMENT - The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit. | 12-26-2013 |
20140245097 | CODEWORDS THAT SPAN PAGES OF MEMORY - The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword. | 08-28-2014 |
20140297990 | MEMORY ADDRESS TRANSLATION - The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address. | 10-02-2014 |
20140317374 | LOGICAL ADDRESS TRANSLATION - The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range. | 10-23-2014 |
20140325316 | DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS - Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks. | 10-30-2014 |