Mojumder
Niladri Mojumder, San Diego, CA US
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20140282330 | PRIORITY BASED LAYOUT VERSUS SCHEMATIC (LVS) - An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices. | 09-18-2014 |
Niladri N. Mojumder, West Lafayette, IN US
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20090190426 | CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM ARRAYS - The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided. | 07-30-2009 |
Niladri N. Mojumder, Lafayette, IN US
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20120280338 | SPIN TORQUE MRAM USING BIDIRECTIONAL MAGNONIC WRITING - An apparatus is provided for bidirectional writing. A stack includes a reference layer on a tunnel barrier, the tunnel barrier on a free layer, and the free layer on a metal spacer. The apparatus includes an insulating magnet. A Peltier material is thermally coupled to the insulating magnet and the stack. When the Peltier/insulating magnet interface is cooled, the insulating magnet is configured to transfer a spin torque to rotate a magnetization of the free layer in a first direction. When the Peltier/insulating magnet interface is heated, the insulating magnet is configured to transfer the spin torque to rotate the magnetization of the free layer in a second direction. | 11-08-2012 |
20120281467 | MAGNONIC MAGNETIC RANDOM ACCESS MEMORY DEVICE - A mechanism is provided for bidirectional writing. A structure includes a reference layer on top of a tunnel barrier, a free layer underneath the tunnel barrier, a metal spacer underneath the free layer, an insulating magnet underneath the metal spacer, and a high resistance layer underneath the insulating layer. The high resistance layer acts as a heater in which the heater heats the insulating magnet to generate spin polarized electrons. A magnetization of the free layer is destabilized by the spin polarized electrons generated from the insulating magnet. A voltage is applied to change the magnetization of the free layer when the magnetization is destabilized. A polarity of the voltage determines when the magnetization of the free layer is parallel and antiparallel to a magnetization of the reference layer. | 11-08-2012 |
Niladri N. Mojumder, Fishkill, NY US
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20130341723 | MEMORY CELL WITH ASYMMETRIC READ PORT TRANSISTORS - A memory cell includes a storage element and a read port. The read port includes a first transistor having a first gate coupled to the storage element, a first source region, and a first drain region. The second transistor includes a second gate, a second source region coupled to the first drain region, and a second drain region. A first dopant profile of the first and second source regions is asymmetric with respect to a second dopant profile of the first and second drain regions. | 12-26-2013 |
Niladri Narayan Mojumder, San Diego, CA US
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20150115473 | HETEROGENEOUS CHANNEL MATERIAL INTEGRATION INTO WAFER - Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device. | 04-30-2015 |