Woeste
Dana M. Woeste, Mantorville, MN US
Patent application number | Description | Published |
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20080205570 | Unlock Mode in Source Synchronous Receivers - A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state. | 08-28-2008 |
Dana Marie Woeste, Mantorville, MN US
Patent application number | Description | Published |
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20090189671 | Method and Apparatus for Improvement of Matching FET Currents Using a Digital to Analog Converter - A method and apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs. | 07-30-2009 |
20090193372 | Design Structure for Improvement of Matching FET Currents Using a Digital to Analog Converter - A design structure comprising apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs. | 07-30-2009 |
Govert Woeste, Dusseldorf DE
Patent application number | Description | Published |
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20100047520 | PLASTICS COMPOSITE MOULDING WITH A THREE-LAYER STRUCTURE - The invention relates to plastics composite mouldings, in particular for the interior trim of motor vehicles, with a three-layer structure comprising a non-foamed support element and a surface layer with an adhesion-modified functional layer arranged between the support element and surface layer. | 02-25-2010 |