Patent application number | Description | Published |
20080230847 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films | 09-25-2008 |
20090184424 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer. | 07-23-2009 |
20090189245 | SEMICONDUCTOR DEVICE WITH SEAL RING - A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner. | 07-30-2009 |
20090263963 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film. | 10-22-2009 |
20100151673 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %. | 06-17-2010 |
20100327449 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %. | 12-30-2010 |
20110001246 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films | 01-06-2011 |
20120289032 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed. Over the main surface, insulating films | 11-15-2012 |
Patent application number | Description | Published |
20100314620 | SEMICONDUCTOR DEVICE - To suppress or prevent the generation of a crack in an insulating film below an external terminal which could be caused by an external force added to the external terminal of a semiconductor device. A top wiring layer MH of wiring layers formed on a main surface of a silicon substrate has a pad comprising a conductor pattern containing aluminum. On an undersurface of the pad, there are arranged a barrier conductor film formed by laminating, from below, a first barrier conductor film and a second barrier conductor film. Of a fifth wiring layer which is one layer lower than the top wiring layer, in an area overlapping with a probe contact area of the pad in a plane, the conductor pattern is not arranged. Further, the first and second barrier conductor films are the conductor films including titanium and titanium nitride as principal components, respectively. Also, the first barrier conductor film is thicker than the second barrier conductor film. | 12-16-2010 |
20110266679 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M | 11-03-2011 |
20130241067 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer. | 09-19-2013 |
Patent application number | Description | Published |
20100078213 | METHOD FOR MANUFACTURING PRINTED WIRING BOARD AND PRINTED WIRING BOARD - A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections. | 04-01-2010 |
20100108371 | WIRING BOARD WITH BUILT-IN ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - A wiring board with a built-in electronic component in which an electronic component is flip-chip mounted to be built in, including a conductive-pattern layer, a connection terminal formed in the conductive-pattern layer and electrically connected to the electronic component, and a solder resist layer formed on the conductive-pattern layer. The solder resist layer is formed around the connection terminal on the conductive-pattern layer, but it is not formed in at least part of the other region on the conductive-pattern layer. | 05-06-2010 |
20100236822 | WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A wiring board is formed with a substrate, conductive patterns laminated in the thickness direction of the substrate, multiple pads having a predetermined pitch and formed on the same layer as the conductive patterns, a conductive bonding layer arranged on each of the multiple pads, and an electronic component having electrodes. Here, the electronic component is arranged inside the substrate. The electrodes of the electronic component and the multiple pads are electrically connected to each other by means of bonding layers. Also, the height of each of the multiple pads is greater than the height of the conductive pattern adjacent to each pad. Moreover, a protective material related to the bonding layers is not formed at least on the layer where the pads and the first conductive patterns are formed. | 09-23-2010 |
20110139498 | PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A printed wiring board including an insulation layer made of a resin material and having first and second surfaces, the insulation layer having an opening portion opened on the second surface, a conductive circuit having first and second surfaces, the conductive circuit being embedded in the insulation layer such that the first surface of the conductive circuit is formed flush with the first surface of the insulation layer and that the second surface of the conductive circuit is exposed through the opening portion of the insulation layer, a first surface-treatment film formed on the conductive circuit and facing the first surface of the conductive circuit, and a second surface-treatment film formed on the conductive circuit and facing the second surface of the conductive circuit and in the opening portion of the insulation layer. | 06-16-2011 |
20120199389 | METHOD FOR MANUFACTURING PRINTED WIRING BOARD AND PRINTED WIRING BOARD - A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections. | 08-09-2012 |
20130215586 | WIRING SUBSTRATE - A wiring substrate includes a motherboard including insulation layers, conductive layers and interlayer connection conductors, a packaging substrate mounted to the motherboard and having through-hole conductors, pads positioned to mount a semiconductor, uppermost via conductors connecting the through-hole conductors and the pads for the semiconductor, pads positioned to connect a motherboard and lowermost via conductors connecting the through-hole conductors and the pads for the motherboard, and bonding members interposed between the motherboard and packaging substrate and connecting the pads for the motherboard and an outermost conductive layer of the motherboard facing the packaging substrate. The pads for the motherboard, lowermost via conductors, through-hole conductors, uppermost via conductors, bonding members and interlayer connection conductors include a pad, a lowermost via conductor, a through-hole conductor, a bonding member and a stacked interlayer connection conductor structure which are positioned to align in a straight line. | 08-22-2013 |
20130221505 | PRINTED WIRING BOARD - A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup. | 08-29-2013 |
20140014399 | PRINTED WIRING BOARD - A printed wiring board includes a core substrate, first and second buildup structures on surfaces of the core, respectively, and first and second solder-resist layers on the first and second structures, respectively. The core includes insulative substrate, conductive layers on surfaces of the substrate and through-hole conductor connecting the conductive layers, the first structure includes interlayer insulation layer and conductive layer in the first structure, the second structure includes interlayer insulation layer and conductive layer in the second structure, a thickness between the outer surfaces of the first and second solder-resist layers is set in range of from 150 μm or greater and less than 380 μm, and at least one of the core, first and second structures, and first and second solder-resist layers includes reinforcing material in amount such that the board includes the material in amount in range of from 20 to 35 vol. %. | 01-16-2014 |