Patent application number | Description | Published |
20080272423 | Conductive structures, non-volatile memory device including conductive structures and methods of manufacturing the same - Conductive structures in an integrated circuit device including an integrated circuit substrate and first conductive layer patterns on the substrate. Second conductive layer patterns are on the substrate extending between respective ones of the first conductive layer patterns. Adjacent ones of the first and second conductive layer patterns are on different horizontal planes relative to the substrate to reduce parasitic capacitance therebetween. | 11-06-2008 |
20080283902 | Non-volatile memory device and method of manufacturing the same - A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components. | 11-20-2008 |
20080296657 | Non-Volatile Memory Devices and Methods of Manufacturing Non-Volatile Memory Devices - A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction. | 12-04-2008 |
20080303079 | Non-volatile Memory Cells Including Fin Structures - A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed. | 12-11-2008 |
20080310238 | Methods of Programming Data in a Non-Volatile Memory Device and Methods of Operating a Nand Flash Memory Device Using the Same - Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate. | 12-18-2008 |
20090008700 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics. | 01-08-2009 |
20090052251 | INTEGRATED CIRCUIT MEMORY DEVICES INCLUDING MEMORY CELLS ON ADJACENT PEDESTALS HAVING DIFFERENT HEIGHTS, AND METHODS OF FABRICATING SAME - Coupling among adjacent rows of memory cells on an integrated circuit substrate may reduced by forming the adjacent rows of memory cells on adjacent semiconductor pedestals that extend different distances away from the integrated circuit substrate. NAND flash memory devices that include different pedestal heights and fabrication methods for integrated circuit memory devices are also disclosed. | 02-26-2009 |
20090146291 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a semiconductor chip including a semiconductor substrate and a plurality of cell transistors arranged on the semiconductor substrate. Channel regions of the cell transistors have channel lengths that extend in a first direction, and the package further includes a supporting substrate having an upper surface on which the semiconductor chip is affixed. The supporting substrate is configured to bend in response to a temperature increase in a manner that applies a tensile stress to the channel regions of the semiconductor chip in the first direction. Related methods are also disclosed. | 06-11-2009 |
20090170271 | TRANSISTOR AND METHOD OF FORMING THE SAME - According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage. | 07-02-2009 |
20090189217 | Semiconductor Memory Devices Including a Vertical Channel Transistor - Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region. | 07-30-2009 |
20090194805 | Non-Volatile Memory Device - A non-volatile memory device includes a substrate, an active region, an isolation layer, a tunnel insulation layer, a floating gate, a dielectric layer and a control gate. The active region includes an upper active region having a first width, and a lower active region beneath the upper active region and having a second width substantially larger than the first width. The isolation layer is adjacent to the active region. The tunnel insulation layer is on the upper active region. The floating gate is on the tunnel insulation layer and has a third width substantially larger than the first width. The dielectric layer is on the floating layer. The control gate is on the dielectric layer. | 08-06-2009 |
20090253243 | Methods of Manufacturing Non-Volatile Memory Devices - In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern. | 10-08-2009 |
20090309154 | SELECTION TRANSISTOR - Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region. | 12-17-2009 |
20100020601 | Multi-Bit Flash Memory Devices and Methods of Programming and Erasing the Same - A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero. | 01-28-2010 |
20100065907 | FIN FET AND METHOD OF FABRICATING SAME - A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode. | 03-18-2010 |
20100085812 | Nonvolatile Memory Devices Having Common Bit Line Structure - Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings. A first string selection line is connected to one of the first and second selection transistors of a first memory string of one pair of memory strings that are connected to one of the common bit lines. A second string selection line is connected to one of the first and second selection transistors of a second memory string of one pair of memory strings that are connected to one of the common bit lines. Multiple word lines are connected to control gates of the unit elements having the NAND cell array structure which are arranged in the same rows. | 04-08-2010 |
20100285645 | METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES - Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region. | 11-11-2010 |
20110170356 | Methods of Programming Data in a Non-Volatile Memory Device and Methods of Operating a Nand Flash Memory Device Using the Same - Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate. | 07-14-2011 |
20110260227 | FIN FET AND METHOD OF FABRICATING SAME - A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode. | 10-27-2011 |
20120181604 | FIN FET AND METHOD OF FABRICATING SAME - A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode. | 07-19-2012 |