Patent application number | Description | Published |
20100309231 | METHOD FOR ADJUSTING THE SETTINGS OF A REPRODUCTION COLOR DEVICE - According to this method, successive iterations are launched according to the following steps:—1) the reproduction color device is set according to settings,—2) reference input colors are calibrated putting calibrated input colors,—4) reproduction quality rating value are calculated,—5) a reproduction quality criterion is applied to decide or not to go for another iteration with different settings. This method allows the optimization of the settings according to color preferences. | 12-09-2010 |
20110122161 | DISPLAY CHARACTERIZATION WITH FILTRATION - A display and a method of characterizing a display includes a means of enabling the display to be measured by a characterization system having a measurement sensor that measures a difference between display characteristics and target values of a screen. The screen is provided with at least a first filter. The first filter is a color correction filter that decreases the difference between the display characteristics and the target values of the screen. | 05-26-2011 |
20110148907 | Method and system for image display with uniformity compensation - A method and system are provided for image display with color transformations that also compensate for non-uniformities in different regions of a display. The method involves performing color measurements at different locations or zones of a display, and deriving respective compensation factors based on these measurements and corresponding target color values, such as those associated with a reference display. These zone- or location-specific compensation factors can be used to derive appropriate compensation factors for arbitrary pixels in an image, which are then used for color transformation of the pixels for display. | 06-23-2011 |
20110154426 | METHOD AND SYSTEM FOR CONTENT DELIVERY - A method and system of content delivery provide availability of at least two versions of content by delivering data for a first version of content, a difference data representing at least one difference between the first version and a second version of content, and metadata derived from two transformation functions that relate the first version and the second version of content respectively to a master version. | 06-23-2011 |
Patent application number | Description | Published |
20080261450 | PORTABLE AND RETRACTABLE FLASH DRIVE WITH OPTIONAL ROTARY DEPLOYING AND RETRACTING AND FINGERPRINT VERIFICATION CAPABILITY - In one embodiment of the present invention a portable and retractable flash drive with optional rotary deploying and retracting and fingerprint verification capability is disclosed to include a cylinder assembly. The cylinder assembly has a connector situated on one end, and a fingerprint sensor situated the surface. The portable and retractable flash drive with optional rotary deploying and retracting and fingerprint verification capability further includes a rotary tube at least partially enclosing the cylinder assembly for deploying the connector. An end tube is rotatably attached to one of the two ends of the rotary tube, and an end cap is attached to the other of the two ends of the rotary tube. The rotary tube is rotated relative to the end tube to slide the cylinder assembly back and forth inside the rotary tube to extend and retract the connector. | 10-23-2008 |
20080278902 | Universal Serial Bus (USB) Flash Drive with Swivel Cap Functionalities with Two Locking Positions - A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end, and a swivel “strap shaped” metal cap having a circle cut out disposed on both cap legs. The snap coupling circle attachment allows the swivel cap to rotate substantially into a first and a second locking position and to rotate substantially 360 degrees about the z-axis of the USB device. The metal cap is generally in a locked position when the snap slot is aligned atop the snap lock tabs such that the protrusion snap ring is descended downward until the positioned flush against the snap lock groove. When unlocked the protrusion snap ring is raised up and rested upon the two snap lock tabs. | 11-13-2008 |
20080278903 | Package and Manufacturing Method for Multi-Level Cell Multi-Media Card - An embodiment of the present invention includes an electronic data flash memory card (memory card) comprising a top cover (TC), a printed circuit board assembly (PCBA) and a bottom cover (BC). The TC includes a plurality of ultrasonic bonders, a plurality of breakaway tabs (tabs) and a connection device. The PCBA includes at least one memory integrated circuit (IC) and at least one controller IC. The BC includes a plurality of tabs. | 11-13-2008 |
20080280490 | Press/Push Universal Serial Bus (USB) Flash Drive with Deploying and Retracting Functionalities with Elasticity Material and Fingerprint Verification Capability - Briefly, an embodiment of the present invention includes a portable flash memory drive with a simplified mechanism, based upon the resilient properties of the material used to create the parts, for reliable extension and retraction of the device's interface plug. The portable flash memory drive is comprised of a metal housing (or case), a printed circuit board (PCB) assembly, PCB support, PCB assembly end cap, an upper, and lower housing, and in some embodiments a fingerprint sensor and/or key ring assembly. The press/push switch mechanism is located on either the side of the portable flash memory device, or the top; and relies upon the resilient properties of the material used to create the metal housing or end cap, to create a smooth, locking mechanism for the extension or retraction of the interface (i.e., USB or firewire) plug. The switching/locking mechanism relies upon grooves or notches within the material of the upper and/or lower housing for tracking and locking, coupled with protrusion tabs on the sliding components of the end cap or metal housing. Alternatively, in some embodiments of the present invention, a fingerprint sensor is also extended or retracted contemporaneously with the interface plug, and allows the end user to secure and unlock the data contained, in whole or in part, therein. | 11-13-2008 |
20080282128 | Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance - An electronic data storage device having a Reed Solomon (RS) decoder including a syndrome calculator block responsive to information including data and overhead and operative to generate a syndrome, in accordance with an embodiment of the present invention. The electronic data storage device further includes a root finder block coupled to receive said syndrome and operative to generate at least two roots, said RS decoder for processing said two roots to generate at least one error address identifying a location in said data wherein said error lies; and an erasure syndrome calculator block responsive to said information and operative to generate an erasure syndrome, said RS decoder responsive to said information identifying a disk crash, said RS decoder for processing said erasure syndrome to generate an erasure error to recover the data in said disk crash. | 11-13-2008 |
Patent application number | Description | Published |
20120044930 | Device initiated DQoS system and method - A Data-Over-Cable Service Interface Specification (DOCSIS) cable modem system is coupled to: i) via a local area internet protocol (IP) network, a voice over internet protocol (VoIP) device operating Session Initiation Protocol (SIP) for signaling a VoIP media session; and ii) via a DOCSIS network, a cable modem termination system (CMTS) via a network. The cable modem system comprises instructions stored in a memory and executed by a processor. The instructions comprise: i) in response to receiving a frame via the local area IP network, determining if the frame is a Session Initiation Protocol (SIP) invite message signaling a VoIP session with a remote endpoint; and ii) in response to determining that the frame is a SIP invite message, generating a DOCSIS message to the CMTS to request an addition of reserved bandwidth on the DOCSIS network for the VoIP session. | 02-23-2012 |
20120047273 | Device initiated multiple grants per interval system and method - A cable modem integrated session border control circuit operates as a point of demarcation between a local area network (LAN) and a DOCSIS network and, in response to receiving a Session Initiation Protocol (SIP) message, which includes Session Description Protocol (SDP), from a VoIP device coupled to the LAN, communicates with a Cable Modem Termination System (CMTS) to take advantage of DOCSIS Dynamic Quality of Service (DQoS) if a VoIP session between the VoIP device and a remote endpoint includes use of the DOCSIS network. The cable modem integrated session border controller further determines required service flow attributes. If required service flow attributes, as determined from the SDP of the SIP message, matches service flow attributes of an existing UGS service flow with a CMTS, a DOCSIS Dynamic Service Chance (DSC) request is used to add an additional sub flow to the existing UGS service flow. If attributes fail to match attributes of all existing UGS service flows, a DOCSIS Dynamic Service Change (DSC) request is used to initiate an additional UGS service flow with the required service flow attributes. | 02-23-2012 |
20120294147 | Device Initiated DQoS System and Method - A Data Over Cable Service Interface Specification (DOCSIS) cable modem system is coupled to: i) via a local area internet protocol (IP) network, a voice over internet protocol (VoIP) device operating Session Initiation Protocol (SIP) for signaling a VoIP session; and ii) via a DOCSIS network, a cable modem termination system (CMTS) via a network. The cable modem system comprises instructions stored in a memory and executed by a processor. The instructions comprise: i) in response to receiving a frame via the local area IP network, determining if the frame is a Session Initiation Protocol (SIP) invite message signaling a VoIP session with a remote endpoint; and ii) in response to determining that the frame is a SIP invite message, generating a DOCSIS message to the CMTS to request an addition of reserved bandwidth on the DOCSIS network for the VoIP session. | 11-22-2012 |
Patent application number | Description | Published |
20140071859 | LOW DUTY CYCLE NETWORK CONTROLLER - Operating at least one low duty cycle (LDC) controller to maintain synchronization between the LDC controller and a plurality of LDC terminals operating over a communication network using only overhead channels of the network and conforming to the protocol and timing of said network, wherein synchronization between the LDC controller and the plurality of LDC terminals is maintained separately from the protocol and timing of the communication network, and enables the LDC controller to schedule power down and wake up of the plurality of LDC terminals for durations longer than allowable under the protocol and timing of the communication network. | 03-13-2014 |
20140114616 | SYSTEM AND METHOD FOR PARAMETERIZING SIGNALS WITH FINITE-RATES-OF-INNOVATION - Systems and methods are described herein for defining and parameterizing signals or system responses with finite rate of innovation (FRI) signal processing. A delta-sigma modulator is used at a low sampling rate to digitize an analog signal for FRI processing. This allows for reduced or eliminated analog pre-filtering while still utilizing low sample rates for an overall reduction in circuit size and power dissipation over conventional FRI signal acquisition techniques. | 04-24-2014 |
20150017951 | SYSTEM AND METHOD OF ASSOCIATING DEVICES BASED ON ACTUATION OF INPUT DEVICES AND SIGNAL STRENGTH - Various operations may be performed based on a distance-related function associated with two or more devices. For example, an association procedure for two or more devices may be based on one or more determined distances. Similarly, presence management may be based on one or more determined distances. A distance-related function may take various form including, for example, a distance between devices, two or more distances between devices, a rate of change in a relative distance between devices, relative acceleration between devices, or some combination of two or more of the these distance-related functions. | 01-15-2015 |
20150024689 | SYSTEM AND METHOD FOR ASSOCIATING DEVICES BASED ON BIOMETRIC INFORMATION - Various operations may be performed based on a distance-related function associated with two or more devices. For example, an association procedure for two or more devices may be based on one or more determined distances. Similarly, presence management may be based on one or more determined distances. A distance-related function may take various form including, for example, a distance between devices, two or more distances between devices, a rate of change in a relative distance between devices, relative acceleration between devices, or some combination of two or more of the these distance-related functions. | 01-22-2015 |
20150103146 | CONVERSION OF AT LEAST ONE NON-STEREO CAMERA INTO A STEREO CAMERA - Methods, apparatuses, and devices are described for converting non-stereo cameras into a stereo camera. At least one optical element may be used to temporarily change an effective position and an effective orientation of a first non-stereo camera. The changed effective position may be displaced from an effective position of a second non-stereo camera by a predetermined distance, and the changed effective orientation may provide the first non-stereo camera with a field of view that overlaps a field of view of the second non-stereo camera. The at least one optical element may be used to capture a first image with the first non-stereo camera. A second image may be captured with the second non-stereo camera. The second image may have a frame of reference displaced from a frame of reference of the first image by the predetermined distance. | 04-16-2015 |
20150163658 | SYSTEM AND METHOD FOR ENABLING OPERATIONS BASED ON DISTANCE TO AND MOTION OF REMOTE DEVICE - Various operations may be performed based on a distance-related function associated with two or more devices. For example, an association procedure for two or more devices may be based on one or more determined distances. Similarly, presence management may be based on one or more determined distances. A distance-related function may take various form including, for example, a distance between devices, two or more distances between devices, a rate of change in a relative distance between devices, relative acceleration between devices, or some combination of two or more of the these distance-related functions. | 06-11-2015 |
Patent application number | Description | Published |
20100312517 | Test Method Using Memory Programmed with Tests and Protocol To Communicate between Device Under Test and Tester - In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported. | 12-09-2010 |
20110113167 | Command Queue for Peripheral Component - In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands. | 05-12-2011 |
20120124243 | Command Queue for Peripheral Component - In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands. | 05-17-2012 |
20120144277 | Two Dimensional Data Randomization for a Memory - In an embodiment, a data scramble/descramble circuit for a memory may employ multiple scramble circuits that may provide randomization of data across both rows and columns of a memory array. The first circuit may receive at least a portion of the address of the row, and may produce an output value by logically operating on the portion of the address. The second circuit may receive the output of the first circuit (or a portion thereof) as a seed, and may scramble the data to be written to memory. In one embodiment, a least significant portion of the address may be operated upon by the first circuit (e.g. the least significant byte), which may be most likely to change from row to row as compared to other portions of the address. | 06-07-2012 |
20130054875 | High Priority Command Queue for Peripheral Component - In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue. | 02-28-2013 |
20130080660 | COMMAND QUEUE FOR PERIPHERAL COMPONENT - In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands. | 03-28-2013 |
20130176787 | Method and Apparatus for Training a DLL in a Memory Subsystem - A method and apparatus for training a DLL in a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory coupled to convey data read therefrom on one or more channels. Each memory channel may include a delay locked loop (DLL) configured to apply a desired amount of delay to a data strobe signal received from the memory during a read operation. Upon detecting a read request, a controller may initiate a training procedure in which the DLL is trained to the desired delay. During the training procedure, an input clock signal may be provided to the DLL. The delay within the DLL may be adjusted until an output clock signal has a desired phase relationship with the input clock signal. Once the desired phase relationship is attained, the training procedure may be terminated and the DLL input may be switched to receive the data strobe signal. | 07-11-2013 |
20130179614 | Command Abort to Reduce Latency in Flash Memory Access - In an embodiment, a peripheral component may include a command queue configured to store a set of commands to perform a transfer on a peripheral interface. Some of the commands may be long-latency commands, and the long-latency commands may be aborted to perform higher priority commands. In an embodiment, each command may have an abort attribute assigned by software which indicates whether or not the command is abortable. If a higher priority command needs to be performed while the long-latency command is in progress, the command may be aborted. In an embodiment, software may write an abort field in a control register to cause the long-latency command to be aborted. | 07-11-2013 |
20130191693 | Trace Queue for Peripheral Component - In an embodiment, a peripheral component may include multiple sources of commands, such as command queues and/or macro memories. The commands may be performed in the peripheral component and may result in an error. The peripheral component may include a trace queue into which the commands may be written, independent of the source of the commands. Thus, the trace queue may provide a record of recently performed commands. | 07-25-2013 |
20140015573 | METHOD AND APPARATUS TO AUTOMATICALLY SCALE DLL CODE FOR USE WITH SLAVE DLL OPERATING AT A DIFFERENT FREQUENCY THAN A MASTER DLL - A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction. | 01-16-2014 |
Patent application number | Description | Published |
20120089712 | SYSTEMS AND METHODS FOR PROVIDING NETWORK RESOURCE ADDRESS MANAGEMENT - Systems and methods are provided for allowing a user to obtain an intended network resource address. An undesired network resource address (NRA) which had been mistakenly entered by a user may be identified as being undesired. In response, an intended NRA may be determined and provided to the user. For example, a database of undesired NRAs may be access to determine an intended NRA (e.g., based on an association of the undesired NRA with an intended NRA). The undesired NRA database may be located local to or remote from the user equipment. The NRA database may be updated in response to, for example, receiving an undesired address command from the user. | 04-12-2012 |
20120176087 | PORTABLE USER DEVICE WITH A CLIP HAVING ELECTRICAL TERMINALS - Systems and methods are provided for docking a portable user device to a docking device or adapter via a clip mechanism. A portable user device may include two clip members which rotate relative to one another about an axis. A coupling pivot may be coupled to both clip members to facilitate relative rotation, and may provide a clamping force between the clip members. One or more terminals may be located on at least one of the clip members, allowing data transfer, charging, or other functions when the portable user device is docked using the clip mechanism. | 07-12-2012 |
20120176504 | SYSTEMS AND METHODS FOR PROVIDING TIMESTAMPING MANAGEMENT FOR ELECTRONIC PHOTOGRAPHS - Systems and methods are provided for revising the time associated with a digital photograph. A digital photograph and data representing an initial time the photograph was taken may not correspond with identified temporal information. In response, a revised time may be generated based on the temporal information and associated with the digital photograph. | 07-12-2012 |
20130275353 | SYSTEMS AND METHODS FOR SELECTING MEDIA ITEMS - Systems and methods are provided for selecting media items for playing on a user media device and generating a playlist of media items based on factors such as the operating state of the user media device, a predicted change in the operating state of the media player device associated with playing or retrieving the media item, and the desirability of the media item to the user. | 10-17-2013 |
Patent application number | Description | Published |
20100221716 | Classification of Nucleic Acid Templates - Methods, compositions, and systems are provided for characterization of modified nucleic acids. In certain preferred embodiments, single molecule sequencing methods are provided for identification of modified nucleotides within nucleic acid sequences. Modifications detectable by the methods provided herein include chemically modified bases, enzymatically modified bases, abasic sites, non-natural bases, secondary structures, and agents bound to a template nucleic acid. | 09-02-2010 |
20110183320 | CLASSIFICATION OF NUCLEIC ACID TEMPLATES - Methods, compositions, and systems are provided for characterization of modified nucleic acids. In certain preferred embodiments, single molecule sequencing methods are provided for identification of modified nucleotides within nucleic acid sequences. Modifications detectable by the methods provided herein include chemically modified bases, enzymatically modified bases, abasic sites, non-natural bases, secondary structures, and agents bound to a template nucleic acid. | 07-28-2011 |
20130029853 | CLASSIFICATION OF NUCLEIC ACID TEMPLATES - Methods, compositions, and systems are provided for characterization of modified nucleic acids. In certain preferred embodiments, single molecule sequencing methods are provided for identification of modified nucleotides within nucleic acid sequences. Modifications detectable by the methods provided herein include chemically modified bases, enzymatically modified bases, abasic sites, non-natural bases, secondary structures, and agents bound to a template nucleic acid. | 01-31-2013 |
20130316916 | CLASSIFICATION OF NUCLEIC ACID TEMPLATES - Methods, compositions, and systems are provided for characterization of modified nucleic acids. In certain preferred embodiments, single molecule sequencing methods are provided for identification of modified nucleotides within nucleic acid sequences. Modifications detectable by the methods provided herein include chemically modified bases, enzymatically modified bases, abasic sites, non-natural bases, secondary structures, and agents bound to a template nucleic acid. | 11-28-2013 |
Patent application number | Description | Published |
20080198941 | LOW-COMPLEXITY SCALABLE ARCHITECTURE FOR CONCATENATION-ASSISTED SYMBOL-LEVEL COMBINING - Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where a receiver has received one or more signal vectors from the same transmitted vector. The receiver processes these received signal vectors one by one, and uses information from signal vectors that have already been processed to process the next signal vector. To process a current signal vector, the receiver concatenates the current signal vector with a previously processed signal vector. This concatenated signal vector is decoded using, for example, a maximum-likelihood (ML). To decode the concatenated signal vector, the ML decoder can use a concatenated channel matrix that includes a channel response matrix associated with the current signal vector and a processed version of previous channel response matrices. | 08-21-2008 |
20080279317 | BICM DECODING IN THE PRESENCE OF CO-CHANNEL INTERFERENCE - Systems and methods are provided for computing soft information for digital information based on a received signal, where the received signal suffers from noise and interference. A receiver that decodes the received signal may estimate channel information, such as the channel gain, associated with the interfering source. The receiver may also obtain modulation information through a backbone network or by decoding control information transmitted by the interfering source. Using the modulation information and the channel information, the receiver may estimate the effect that interference has on the received signal, and may compute soft information (e.g., a log-likelihood ratio) for the digital information. | 11-13-2008 |
20090051592 | Pseudo-Omni-Directional Beamforming with Multiple Narrow-Band Beams - In a technique for communication with a station on a wireless network, the technique includes forming a plurality of narrow-band beams, each having a different angular direction from an antenna of a base station and collectively distributed over a beamspace to form a pseudo-omni-directional beam pattern. That beamspace may span an entire spherical region or a portion thereof, for example, when the narrow-band beams are broadcast over a sector of an entire spherical region. The technique may assign each of the plurality of narrow-band beams to a different frequency band (such as a different channel band or sub-channel) on the wireless network. The technique may simultaneously broadcast the plurality of narrow-band beams in a time-varying manner such that the angular direction of each of the plurality of narrow-band beams varies with time, where that variation may be random or ordered. | 02-26-2009 |
20090262855 | DATA SYMBOL MAPPING FOR MULTIPLE-INPUT MULTIPLE-OUTPUT HYBRID AUTOMATIC REPEAT REQUEST - A system includes an encoding module, a symbol selection module, a subcarrier selection module, and a mapping module. The encoding module receives symbols for transmission over K subcarriers and T antennas, encodes the symbols using a space time code, and generates space time coded (STC) versions of the symbols, where K and T are integers greater than 1. The symbol selection module selects T adjacent ones of the symbols and selects STC versions of the T adjacent ones of the symbols. The subcarrier selection module selects one of the K subcarriers for transmitting the T adjacent ones of the symbols and the STC versions of the T adjacent ones of the symbols. The mapping module maps the T adjacent ones of the symbols onto the T antennas for transmission over the selected one of the K subcarriers, respectively, and maps the STC versions of the T adjacent ones of the symbols onto the T antennas for transmission over the selected one of the K subcarriers. | 10-22-2009 |
20090279633 | SYMBOL VECTOR-LEVEL COMBINING TRANSMITTER FOR INCREMENTAL REDUNDANCY HARQ WITH MIMO - Techniques are provided for transmitting and receiving a mother code in an incremental redundancy hybrid automatic repeat-request protocol. A set of information bits corresponding to a message may be encoded and interleaved to produce the mother code. Each bit position of the mother code may be mapped to an output symbol, and each output symbol may be mapped to an antenna for transmission. One or more transmissions of symbols contained in the output symbols may be performed, where each transmission may include puncturing the mother code by selecting one or more symbols from the of output symbols, and transmitting each symbol in the one or more symbols on an antenna corresponding to that symbol. The mother code may be decoded, in part, by determining combinable bits contained within a set of received symbols, and computing one or more log-likelihood ratio values corresponding to each symbol in the set of received symbols. | 11-12-2009 |
20090282311 | SYMBOL VECTOR-LEVEL COMBINING RECEIVER FOR INCREMENTAL REDUNDANCY HARQ WITH MIMO - Techniques are provided for transmitting and receiving a mother code in an incremental redundancy hybrid automatic repeat-request protocol. A set of information bits corresponding to a message may be encoded and interleaved to produce the mother code. Each bit position of the mother code may be mapped to an output symbol, and each output symbol may be mapped to an antenna for transmission. One or more transmissions of symbols contained in the output symbols may be performed, where each transmission may include puncturing the mother code by selecting one or more symbols from the of output symbols, and transmitting each symbol in the one or more symbols on an antenna corresponding to that symbol. The mother code may be decoded, in part, by determining combinable bits contained within a set of received symbols, and computing one or more log-likelihood ratio values corresponding to each symbol in the set of received symbols. | 11-12-2009 |
20100005357 | Symbol Vector Mapping for Chase-Combining HARQ - A method of transmitting data from a transmitter to a receiver includes transmitting a first data unit to the receiver via a plurality of antennas, the first data unit including a payload that has a plurality of symbols; determining whether the receiver has successfully received the first data unit; and, in response to determining that the receiver has not successfully received the first data unit, transmitting a second data unit to the receiver, the second data unit including the payload, such that transmitting die second data unit includes transmitting the plurality of symbols via at least one of different antennas and different subcarriers with respect to the first data unit. | 01-07-2010 |
20120069935 | SYMBOL-LEVEL COMBINING FOR MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) SYSTEMS WITH HYBRID AUTOMATIC REPEAT REQUEST (HARQ) AND/OR REPETITION CODING - Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The symbols of the received signal vectors are combined, forming a combined received signal vector that may be treated as a single received signal vector. The combined signal vector is then decoded using a maximum-likelihood decoder. In some embodiments, the combined received signal vector may be processed prior to decoding. Systems and methods are also provided for computing soft information from a combined signal vector based on a decoding metric. Computationally intensive calculations can be extracted from the critical path and implemented in preprocessors and/or postprocessors. | 03-22-2012 |
20120121005 | CONCATENATION-ASSISTED SYMBOL-LEVEL COMBINING FOR MIMO SYSTEMS WITH HARQ AND/OR REPETITION CODING - Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The receiver combines the received vectors by vector concatenation The concatenated vector may then be decoded using, for example, maximum-likelihood decoding. In some embodiments, the combined signal vector is equalized before decoding. | 05-17-2012 |
20120202548 | PSEUDO-OMNI-DIRECTIONAL BEAMFORMING WITH MULTIPLE NARROW-BAND BEAMS - In a technique for communication with a station on a wireless network, the technique includes forming a plurality of narrow-band beams, each having a different angular direction from an antenna of a base station and collectively distributed over a beamspace to form a pseudo-omni-directional beam pattern. That beamspace may span an entire spherical region or a portion thereof, for example, when the narrow-band beams are broadcast over a sector of an entire spherical region. The technique may assign each of the plurality of narrow-band beams to a different frequency band (such as a different channel band or sub-channel) on the wireless network. The technique may simultaneously broadcast the plurality of narrow-band beams in a time-varying manner such that the angular direction of each of the plurality of narrow-band beams varies with time, where that variation may be random or ordered. | 08-09-2012 |
20120213316 | PREAMBLE DETECTION WITH UNKNOWN CHANNEL - A system comprises a correlation module that correlates modulated signals with a plurality of preamble sequences and that generates correlation values. A control module selects a largest correlation value from said correlation values and detects one of said preamble sequences in said modulated signals upon determining that a magnitude of said largest correlation value is greater than or equal to a first predetermined threshold. | 08-23-2012 |
20130039447 | SYMBOL VECTOR-LEVEL COMBINING RECEIVER FOR INCREMENTAL REDUNDANCY HARQ WITH MIMO - Techniques are provided for transmitting and receiving a mother code in an incremental redundancy hybrid automatic repeat-request protocol. Each bit position of the mother code may be mapped to an output symbol, and each output symbol may be mapped to an antenna for transmission. One or more transmissions of symbols contained in the output symbols may be performed, where each transmission may include puncturing the mother code by selecting one or more symbols from the of output symbols, and transmitting each symbol in the one or more symbols on an antenna corresponding to that symbol. The mother code may be decoded, in part, by determining combinable bits contained within a set of received symbols, and computing one or more log-likelihood ratio values corresponding to each symbol in the set of received symbols. | 02-14-2013 |
20130235828 | SYMBOL VECTOR MAPPING FOR CHASE-COMBINING HARQ - A method includes mapping, based on a first antenna mapping, a plurality of symbols to a plurality of antennas for transmitting a first data unit to a receiver, mapping, based on a first subcarrier mapping, the plurality of symbols to a plurality of subcarriers for transmitting the first data unit, and determining whether the receiver has successfully received the first data unit. The method also includes, in response to determining that the receiver has not successfully received the first data unit, (i) mapping, based on a second antenna mapping, the plurality of symbols to the plurality of antennas for transmitting a second data unit to the receiver, (ii) mapping, based on a different, second subcarrier mapping, the plurality of symbols to the plurality of subcarriers for transmitting the second data unit, and (iii) causing the second subcarrier mapping to be communicated to the receiver. | 09-12-2013 |
Patent application number | Description | Published |
20130155071 | Document Collaboration Effects - Various features and processes related to document collaboration are disclosed. In some implementations, animations are presented when updating a local document display to reflect changes made to the document at a remote device. In some implementations, a user can selectively highlight changes made by collaborators in a document. In some implementations, a user can select an identifier associated with another user to display a portion of a document that includes the other user's cursor location. In some implementations, text in document chat sessions can be automatically converted into hyperlinks which, when selected, cause a document editor to perform an operation. | 06-20-2013 |
20130159830 | Smart Text in Document Chat - Various features and processes related to document collaboration are disclosed. In some implementations, animations are presented when updating a local document display to reflect changes made to the document at a remote device. In some implementations, a user can selectively highlight changes made by collaborators in a document. In some implementations, a user can select an identifier associated with another user to display a portion of a document that includes the other user's cursor location. In some implementations, text in document chat sessions can be automatically converted into hyperlinks which, when selected, cause a document editor to perform an operation. | 06-20-2013 |
20130159849 | Jump to Collaborator Cursor - Various features and processes related to document collaboration are disclosed. In some implementations, animations are presented when updating a local document display to reflect changes made to the document at a remote device. In some implementations, a user can selectively highlight changes made by collaborators in a document. In some implementations, a user can select an identifier associated with another user to display a portion of a document that includes the other user's cursor location. In some implementations, text in document chat sessions can be automatically converted into hyperlinks which, when selected, cause a document editor to perform an operation. | 06-20-2013 |
20130160142 | Track Changes Permissions - Various features and processes related to document collaboration are disclosed. In some implementations, animations are presented when updating a local document display to reflect changes made to the document at a remote device. In some implementations, a user can selectively highlight changes made by collaborators in a document. In some implementations, a user can select an identifier associated with another user to display a portion of a document that includes the other user's cursor location. In some implementations, text in document chat sessions can be automatically converted into hyperlinks which, when selected, cause a document editor to perform an operation. | 06-20-2013 |
20130174025 | VISUAL COMPARISON OF DOCUMENT VERSIONS - Visual comparison of document versions is described. In some implementations, versions of a document can be quickly displayed using a single user input. In some implementations, a displayed page of a version of the document can be replaced by a corresponding page of another version of the document. | 07-04-2013 |
20140281943 | WEB-BASED SPELL CHECKER - A fast client-side spell checker is provided that builds efficient structures out of dictionary and a common misspelling lists and uses the structures to prune the number of searches required to identify misspelled words and provide suggestions for correcting the misspelled words. The spell checker is a browser-based application, which is provided by a server to a client device. The server also sends the dictionary and a list of common misspellings to the client device in the form of efficient data structures. The spell checker utilizes a set of rules to identify the words that are not in the dictionary but are intended to be correct as typed. The spell checker is used by different browser-based applications that utilize the same spell checker regardless of the browser platform used to access the applications. In this way, the spell checker provides a uniform spell checking user experience across different browser platforms. | 09-18-2014 |
Patent application number | Description | Published |
20090012945 | SYSTEM FOR EXECUTING A QUERY HAVING MULTIPLE DISTINCT KEY COLUMNS - A system and computer readable medium for executing a query to access data stored in a database, wherein the query includes a plurality of DISTINCT keys, is disclosed. The system and computer readable medium includes a capture module for identifying each of the plurality of DISTINCT keys in the query and a sort module coupled to the capture module for determining if more than one sort is needed to execute the query, performing a first DISTINCT operation on a first DISTINCT key of the plurality of DISTINCT keys, storing data fetched from the first DISTINCT operation in a master workfile only if more than one sort process is needed to execute the query, and utilizing the master workfile to perform subsequent DISTINCT operations on the other of the plurality of DISTINCT keys. | 01-08-2009 |
20150074134 | BOOLEAN TERM CONVERSION FOR NULL-TOLERANT DISJUNCTIVE PREDICATES - System, method, and computer program product to modify a received query, the received query including a first predicate specifying a comparison operator and a second predicate specifying an IS NULL operator, by replacing the comparison operator of the first predicate with an extended comparison operator, and removing the IS NULL operator from the received query, the extended comparison operator configured to support searching of NULL values in a database management system (DBMS), wherein the extended comparison operator is configured to return rows having column data matching a value predefined to represent NULL values. | 03-12-2015 |
20150074135 | BOOLEAN TERM CONVERSION FOR NULL-TOLERANT DISJUNCTIVE PREDICATES - System, method, and computer program product to modify a received query, the received query including a first predicate specifying a comparison operator and a second predicate specifying an IS NULL operator, by replacing the comparison operator of the first predicate with an extended comparison operator, and removing the IS NULL operator from the received query, the extended comparison operator configured to support searching of NULL values in a database management system (DBMS), wherein the extended comparison operator is configured to return rows having column data matching a value predefined to represent NULL values. | 03-12-2015 |
Patent application number | Description | Published |
20100199154 | Reduced processing in high-speed Reed-Solomon decoding - Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift. | 08-05-2010 |
20110125959 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored. | 05-26-2011 |
20110239085 | ECC WITH OUT OF ORDER COMPLETION - Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder. | 09-29-2011 |
20120081971 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits. | 04-05-2012 |
20130208540 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - An instruction to perform an erase on a group of one or more memory cells is sent. An indication that the erasure of the group of memory cells is unsuccessful is received. In response to receiving the indication that the erasure of the group of memory cells is unsuccessful, the value of a voltage threshold, associated with the group of memory cells, is changed to a new voltage threshold and the new voltage threshold and identification information associated with the group of memory cells is stored. | 08-15-2013 |
20140219033 | FLASH MULTIPLE-PASS WRITE WITH ACCURATE FIRST-PASS WRITE - An indication to store a data value in Flash memory is received. An accurate coarse write is performed on the Flash memory, including by: storing a first voltage level in the Flash memory and setting a configuration setting of the Flash memory to a first setting. The first voltage level, when interpreted using the configuration setting at the first setting, corresponds to the data value. A fine write is performed on the Flash memory, including by: storing a second voltage level in the Flash memory and setting the configuration setting of the Flash memory to a second setting. The second voltage level, when interpreted using the configuration setting at the second setting, corresponds to the data value. | 08-07-2014 |
20140365716 | INTERFACE BETWEEN MULTIPLE CONTROLLERS - A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface. | 12-11-2014 |
20140376314 | FLASH MULTIPLE-PASS WRITE WITH ACCURATE FIRST-PASS WRITE - An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction. | 12-25-2014 |
20150220277 | FLASH MEMORY COMPRESSION - Systems and method for reading compressed data from non-volatile storage such as an SSD device are disclosed. A logical section, e.g. page, of data includes a plurality of data blocks that are compressed such that the lengths thereof are different. A header section of the page stores headers for the data blocks and storing a length for each data block. The header section may be a codeword encoding the headers according to an error correction scheme. To read out a data block a hardware decoder requests reading of the page and transfers the header section into a hardware decoder that decodes the headers to obtain an offset for a desired data block. Without instructing reading of the page, the offset is used by the hardware decoder to request transfer of the desired data block that is then decoded and returned to a requesting device. | 08-06-2015 |
20150235707 | FLASH MULTIPLE-PASS WRITE WITH ACCURATE FIRST-PASS WRITE - An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction. | 08-20-2015 |
Patent application number | Description | Published |
20080213997 | SELECTIVE COPPER-SILICON-NITRIDE LAYER FORMATION FOR AN IMPROVED DIELECTRIC FILM/COPPER LINE INTERFACE - A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing gas, where the second plasma removes copper oxide from the copper surface, and exposing the wafer to silane, where the silane reacts with the copper surface to selectively form copper silicide. The process may further include exposing the wafer to a third plasma made from ammonia and molecular nitrogen to form the copper silicon nitride layer. | 09-04-2008 |
20090107626 | ADHESION IMPROVEMENT OF DIELECTRIC BARRIER TO COPPER BY THE ADDITION OF THIN INTERFACE LAYER - Embodiments described herein provide a method of processing a substrate. The method includes depositing an interface adhesion layer between a conductive material and a dielectric material such that the interface adhesion layer provides increased adhesion between the conductive material and the dielectric material. In one embodiment a method for processing a substrate is provided. The method comprises depositing an interface adhesion layer on a substrate comprising a conductive material, exposing the interface adhesion layer to a nitrogen containing plasma, and depositing a dielectric layer on the interface adhesion layer after exposing the interface adhesion layer to the nitrogen containing plasma. | 04-30-2009 |
20090269923 | ADHESION AND ELECTROMIGRATION IMPROVEMENT BETWEEN DIELECTRIC AND CONDUCTIVE LAYERS - A method and apparatus for processing a substrate is provided. The method of processing a substrate includes providing a substrate comprising a conductive material, performing a pre-treatment process on the conductive material, flowing a silicon based compound on the conductive material to form a silicide layer, performing a post treatment process on the silicide layer, and depositing a barrier dielectric layer on the substrate. | 10-29-2009 |
20120276301 | ADHESION IMPROVEMENT OF DIELECTRIC BARRIER TO COPPER BY THE ADDITION OF THIN INTERFACE LAYER - Embodiments described herein provide a method of processing a substrate. The method includes depositing an interface adhesion layer between a conductive material and a dielectric material such that the interface adhesion layer provides increased adhesion between the conductive material and the dielectric material. In one embodiment a method for processing a substrate is provided. The method comprises depositing an interface adhesion layer on a substrate comprising a conductive material, exposing the interface adhesion layer to a nitrogen containing plasma, and depositing a dielectric layer on the interface adhesion layer after exposing the interface adhesion layer to the nitrogen containing plasma. | 11-01-2012 |
Patent application number | Description | Published |
20120038809 | DIFFERENTIAL COLUMN ADC ARCHITECTURES FOR CMOS IMAGE SENSOR APPLICATIONS - Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise. | 02-16-2012 |
20120039548 | FRAME-WISE CALIBRATION OF COLUMN-PARALLEL ADCS FOR IMAGE SENSOR ARRAY APPLICATIONS - Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration. | 02-16-2012 |
20120169909 | IMAGE PROCESSING SYSTEM WITH ON-CHIP TEST MODE FOR COLUMN ADCS - An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row. | 07-05-2012 |
20120194252 | METHOD OF SHIFTING AUTO-ZERO VOLTAGE IN ANALOG COMPARATORS - Aspects of the invention provide, inter alia, techniques for shifting auto-zero voltage in analog comparators. An embodiment of the invention may include at least one diode configured transistor to increase a drain voltage of at least one NMOS load transistor. A first switch and a second switch may be implemented to increase a voltage at a gate of a first PMOS input transistor and a voltage at a gate of a second PMOS input transistor when the first switch and the second switch are closed. | 08-02-2012 |
20120194261 | CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS - Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. | 08-02-2012 |
20120194368 | METHOD AND SYSTEM FOR CALIBRATING COLUMN PARALLEL ADCS - Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude. | 08-02-2012 |
20120306674 | AUTOMATIC OFFSET ADJUSTMENT FOR DIGITAL CALIBRATION OF COLUMN PARALLEL SINGLE-SLOPE ADCS FOR IMAGE SENSORS - Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude. | 12-06-2012 |
20150097596 | CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS - Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. | 04-09-2015 |
20150102840 | CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS - Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. | 04-16-2015 |
Patent application number | Description | Published |
20130235003 | GATE LINE DRIVER CIRCUIT FOR DISPLAY ELEMENT ARRAY - Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed. | 09-12-2013 |
20130335658 | Pixel Architecture for Electronic Displays - An electronic display for providing a visual or video output for an electronic device. The electronic device includes a transistor layer configured to activate a first pixel row and a second pixel row. For each pixel in the first pixel row and the second pixel row, the transistor layer includes a switch transistor, a pixel electrode, and a common electrode. The electronic device further includes a pixel controller for selectively activating each pixel. The pixel controller includes a first gate line, a first drive line, and a second drive line. During operation, the first gate line provides a charge to the pixel electrode for a first pixel in the first pixel row and for a second pixel in the second pixel row, and the first drive line activates the switch transistor for the first pixel, and the second drive line activates the switch transistor for the second pixel. | 12-19-2013 |
20140049721 | Displays with Shielding Layers - An electronic device may have a display such as a liquid crystal display. The display may have a color filter layer and a thin-film transistor layer. An opaque masking layer may be formed on the color filter layer. An active portion of the display may contain an array of display pixels that are controlled by control signals that are provided over intersecting gate lines and data lines. In an inactive portion of the display, gate driver circuits may be used to generate gate line signals for the gate lines. Portions of the gate lines in the gate driver circuitry, power supply lines, and common electrode lines may be formed on the thin-film-transistor layer. These lines may be electromagnetically shielded using indium tin oxide shielding layers to prevent electric fields from inducing charge in the opaque masking layer and thereby causing color artifacts. | 02-20-2014 |
20140111496 | Displays with Circuitry for Compensating Parasitic Coupling Effects - An electronic device may have a display such as a liquid crystal display. The display may have a color filter layer and a thin-film transistor (TFT) layer. An active portion of the display may contain an array of display pixels that are controlled by control signals that are provided over intersecting gate lines and data lines. In an inactive portion of the display, display driver circuitry may be used to provide data signals for the data lines. Each display pixel may be coupled to a corresponding gate line, data line, and may share a common electrode. Changes in the data signals may be coupled onto the common electrode to cause voltage rippling. Compensation circuitry may be coupled to the common electrode via an AC or a DC coupling connection to help reduce the voltage rippling. | 04-24-2014 |
20140118666 | Display with Column Spacer Structures Resistant to Lateral Movement - A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor layer. Column spacers may be formed on the color filter layer to maintain a desired gap between the color filter and thin-film transistor layers. Support pads may be used to support the column spacers. Different column spacers may be located at different portions of the support pads to allow the support pad size to be reduced while ensuring adequate support. Lateral movement blocking structures such as circular rings may be used to prevent column spacer lateral movement. Subspacers located over pads may be used to create friction that retards lateral movement. Lateral movement may also be retarded by receiving column spacers in trenches or other recesses formed on a thin-film transistor layer. | 05-01-2014 |
20140327851 | Display Pixels with Improved Storage Capacitance - A display may include one or more display pixels in an array of pixels. A display pixel may include a storage capacitor chat stores a pixel data signal. The storage capacitor may be formed from a pixel electrode structure, a capacitor electrode structure, and a common electrode structure that is interposed between the pixel electrode structure and capacitor electrode structures. Each electrode structure may be formed from transparent conductive materials deposited on respective display layers. The pixel electrode structure and capacitor electrode structure may be electrically coupled by a conductive via structure that extends through the display layers without contacting the common electrode structure. The conductive via structure may contact underlying transistor structures such as a source-drain structure. | 11-06-2014 |
20150054799 | Display Driver Circuitry For Liquid Crystal Displays With Semiconducting-Oxide Thin-Film Transistors - An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure. | 02-26-2015 |
20150055047 | Liquid Crystal Displays with Oxide-Based Thin-Film Transistors - An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure. | 02-26-2015 |
20150220194 | Displays with Intra-Frame Pause - A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing, (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress. | 08-06-2015 |
Patent application number | Description | Published |
20110130958 | DYNAMIC ALERTS FOR CALENDAR EVENTS - A computing device can access a calendar entry having an associated time and an associated location, in a calendar application. The computing device can dynamically determine an estimated travel time to the location associated with the calendar entry. The computing device can provide an alarm indication for the calendar entry at a time based on the estimated travel time. | 06-02-2011 |
20130231864 | DYNAMIC ALERTS FOR CALENDAR EVENTS - A computing device can access a calendar entry having an associated time and an associated location, in a calendar application. The computing device can dynamically determine an estimated travel time to the location associated with the calendar entry. The computing device can provide an alarm indication for the calendar entry at a time based on the estimated travel time. | 09-05-2013 |
20140163882 | DYNAMIC ALERTS FOR CALENDAR EVENTS - A computing device can access a calendar entry having an associated time and an associated location, in a calendar application. The computing device can dynamically determine an estimated travel time to the location associated with the calendar entry. The computing device can provide an alarm indication for the calendar entry at a time based on the estimated travel time. | 06-12-2014 |
20150031336 | System and Method for Providing Telephony Services over WiFi for Non-Cellular Devices - A method performed by a provisioning server, the method including receiving registration data from a client station, transmitting activation data to a telephony service provider, the activation data generated as a function of the registration data, the activation data being used to generate telephony data for the user, the telephony data including access data to utilize a telephony network of the telephony service provider and transmitting the telephony data to the client station, wherein select portions of the telephony data and select portions of the activation data verify the client station as an authenticated device to utilize the telephony network. | 01-29-2015 |
20150245388 | System and Method for Performing Emergency Calls Over WiFi - A station that performs methods related to emergency calls. In one example, the station determines that a first connection to a cellular network is unavailable, the client station being associated with a home network having a home Public-Safety Answering Point (PSAP), the station disposed at a location outside the home network, the location having a remote PSAP. The station determines a second connection to a WiFi network is available, establishes the second connection to the WiFi network and performs an emergency call over the WiFi network. The emergency call being routed to the remote PSAP associated with the location. In another example, the station determines it is capable of performing an emergency call over a cellular network, receives a request to perform an emergency call, determines whether a circuit switched radio access technology (CS-RAT) is available and performs the emergency call over a WiFi network when the CS-RAT is unavailable. | 08-27-2015 |
Patent application number | Description | Published |
20100171152 | INTEGRATED CIRCUIT INCORPORATING DECODERS DISPOSED BENEATH MEMORY ARRAYS - A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate. | 07-08-2010 |
20110019467 | VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION - A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided. | 01-27-2011 |
20110156044 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 06-30-2011 |
20120223380 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 09-06-2012 |
20120250396 | VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION - A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided. | 10-04-2012 |
20130314970 | PILLAR-SHAPED NONVOLATILE MEMORY AND METHOD OF FABRICATION - A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided. | 11-28-2013 |
20140217491 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 08-07-2014 |
20140239248 | THREE-DIMENSIONAL NONVOLATILE MEMORY AND METHOD OF FABRICATION - A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided. | 08-28-2014 |
20150044833 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 02-12-2015 |