Patent application number | Description | Published |
20090187909 | SHARED RESOURCE BASED THREAD SCHEDULING WITH AFFINITY AND/OR SELECTABLE CRITERIA - Threads may be scheduled to be executed by one or more cores depending upon whether it is more desirable to minimize power or to maximize performance. If minimum power is desired, threads may be schedule so that the active devices are most shared; this will minimize the number of active devices at the expense of performance. On the other hand, if maximum performance is desired, threads may be scheduled so that active devices are least shared. As a result, threads will have more active devices to themselves, resulting in greater performance at the expense of additional power consumption. Thread affinity with a core may also be taken into consideration when scheduling threads in order to improve the power consumption and/or performance of an apparatus. | 07-23-2009 |
20100128541 | INTEGRATED CIRCUIT HAVING MEMORY WITH CONFIGURABLE READ/WRITE OPERATIONS AND METHOD THEREFOR - An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin. | 05-27-2010 |
20100188131 | LEVEL SHIFTER FOR CHANGE OF BOTH HIGH AND LOW VOLTAGE - A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first and second supply terminals. The first transistor is coupled to a first power supply terminal, to the output terminal of the second inverter, and to the first inverter. The second transistor is coupled to the first power supply terminal, to the output terminal of the first inverter, and to the first supply terminal of the second inverter. The third and fourth transistor are coupled to the second supply terminals of the first and second inverters, respectively, and each includes a control electrode and a second current electrode. The enabling circuit is for controlling the third and fourth transistors to reduce a leakage current in the circuit. | 07-29-2010 |
20100191990 | VOLTAGE-BASED MEMORY SIZE SCALING IN A DATA PROCESSING SYSTEM - A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased. | 07-29-2010 |
20100246297 | INTEGRATED CIRCUIT HAVING AN EMBEDDED MEMORY AND METHOD FOR TESTING THE MEMORY - A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array. | 09-30-2010 |
20100246298 | INTEGRATED CIRCUIT MEMORY HAVING ASSISTED ACCESS AND METHOD THEREFOR - A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for the weak memory element. The weak memory element is designated as a test element. In response to receiving a request to change a power supply voltage provided to the memory elements, a second test is used to test the test element to determine if the test element will function correctly at a new power supply voltage. If the test element passes the second test, the memory elements are accessed at the new power supply voltage. If the test element fails the second test, the memory elements are accessed using an access assist operation. | 09-30-2010 |
20100277990 | INTEGRATED CIRCUIT HAVING MEMORY REPAIR INFORMATION STORAGE AND METHOD THEREFOR - A storage unit on an integrated circuit stores information that identifies a circuit on the integrated circuit, a selected operating condition, and a required operating configuration for the circuit for the selected operating condition. The manner of operating the circuit is changed to the required operating configuration in response to an operating condition of the circuit changing to the selected operating condition. This allows for efficiently identifying the few circuits that do not meet specified requirements based on a reduction in, for example, operating voltage, and altering their operation in order to meet the specified requirements relative to the reduced operating voltage without having to do so for the vast majority of the circuits that are able to meet the requirements at the lowered operating voltage. | 11-04-2010 |
20100283445 | INTEGRATED CIRCUIT HAVING LOW POWER MODE VOLTAGE REGULATOR - A voltage regulator includes a node, circuitry, a regulating transistor, a disabling transistor, and a voltage follower stage. The circuitry is coupled to the node for providing a current to the node. The regulating transistor is coupled between the node and a first power supply voltage terminal. The disabling transistor is coupled in parallel with the regulating transistor for selectively disabling the regulating transistor by directly connecting the first power supply voltage terminal to the node. The voltage follower stage is coupled between the first power supply voltage terminal and a second power supply voltage terminal. The voltage follower stage has an output connected to a control electrode of the regulating transistor, and an input connected to the node. | 11-11-2010 |
20100302837 | MEMORY WITH READ CYCLE WRITE BACK - A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle. | 12-02-2010 |
20100309736 | SRAM WITH READ AND WRITE ASSIST - A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal. | 12-09-2010 |
20100322027 | MEMORY USING MULTIPLE SUPPLY VOLTAGES - A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is decoupled from the power supply node in response to terminating the first operation of the first type so as to allow the power supply node to drift. If the power supply node drifts to a second voltage, a power supply source is coupled to the power supply node. This is useful in reducing power in the circuit that produces the first voltage. | 12-23-2010 |
20110211383 | INTEGRATED CIRCUIT HAVING VARIABLE MEMORY ARRAY POWER SUPPLY VOLTAGE - An integrated circuit comprises a memory array and a bias circuit. The memory array comprises a plurality of memory cells arranged in a grid of rows and columns. A first conductor is coupled to a power supply voltage terminal of each of the plurality of memory cells. A second conductor is coupled to receive a power supply voltage. The memory array also includes a plurality of dummy cells. A transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode. The bias circuit is coupled to the control electrode of the transistor. | 09-01-2011 |
20110255361 | MULTI-PORT MEMORY HAVING A VARIABLE NUMBER OF USED WRITE PORTS - A multi-port memory is operated according to a method. Data is written, in a first mode, to a storage node of a memory cell from a first port through a first conductance. The first mode is characterized by a power supply voltage being applied at a power node at a first level. Data is written, in a second mode, to the storage node of the memory cell simultaneously from the first port through the first conductance and a second port through a second conductance. The second mode is characterized by the power supply voltage being applied at the power node at a second level different from the first level. | 10-20-2011 |
20120030482 | DATA PROCESSING HAVING MULTIPLE LOW POWER MODES AND METHOD THEREFOR - A method is provided for operating a data processing system having a memory. The memory is coupled between a first power supply voltage terminal for receiving a first variable potential and a second power supply voltage terminal for receiving a second variable potential. An initial difference between the first variable potential and the second variable potential is not less than a first voltage. The method comprises: receiving a command to transition the data processing system from a first power supply voltage to a second power supply voltage; changing the second variable potential so that a difference between the second variable potential and the first variable potential is greater than the first voltage; and after changing the second variable potential, changing the first variable potential, wherein a difference between the first variable potential and the second variable potential is not less than the first voltage. | 02-02-2012 |
20120033520 | MEMORY WITH LOW VOLTAGE MODE OPERATION - A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells. | 02-09-2012 |
20120200336 | ELECTRONIC CIRCUIT HAVING SHARED LEAKAGE CURRENT REDUCTION CIRCUITS - An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits. | 08-09-2012 |
20120230126 | MEMORY VOLTAGE REGULATOR WITH LEAKAGE CURRENT VOLTAGE CONTROL - A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells. | 09-13-2012 |
20130019133 | METHODS FOR TESTING A MEMORY EMBEDDED IN AN INTEGRATED CIRCUIT - A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array. | 01-17-2013 |
20130265818 | WRITE CONTENTION-FREE, NOISE-TOLERANT MULTI-PORT BITCELL - A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter. | 10-10-2013 |
20130268732 | SYSTEM AND METHOD FOR CACHE ACCESS - The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses. | 10-10-2013 |
20130290753 | MEMORY COLUMN DROWSY CONTROL - In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column. | 10-31-2013 |
20130322159 | MULTI-PORT REGISTER FILE WITH MULTIPLEXED DATA - A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first plurality of write ports, a write select signal coupled to the write ports, a plurality of write port address lines coupled as input to each of the write ports, and a first plurality of word line select circuits coupled to receive an address signal and the write select signal for each of the write ports and to provide a single selected write word line signal to a respective one of the rows of the storage devices for one of the first plurality of write ports activated by the write select signal. | 12-05-2013 |
20140003172 | MEMORY WITH WORD LINE ACCESS CONTROL | 01-02-2014 |
20140052924 | Selective Memory Scrubbing Based on Data Type - A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache). | 02-20-2014 |
20140052931 | Data Type Dependent Memory Scrubbing - A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval. | 02-20-2014 |
20140195729 | Memory Having Improved Reliability for Certain Data Types - A method for minimizing soft error rates within caches by configuring a cache with certain sections to correspond to bitcell topologies that are more resistant to soft errors and then using these sections to store modified data. | 07-10-2014 |
20140195733 | Memory Using Voltage to Improve Reliability for Certain Data Types - A method for minimizing soft error rates within caches by configuring a cache with a certain way which is more resistant to soft errors and then using this way to store modified data. In certain embodiments, the memory is made more soft error resistant by increasing a voltage across bitcells of the cache. | 07-10-2014 |
20140269131 | MEMORY WITH POWER SAVINGS FOR UNNECESSARY READS - A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers. | 09-18-2014 |
20140281291 | Method and Apparatus for Memory Array Access - A method includes: receiving a first plurality of consecutive bits from a base operand, wherein a MSB of the first plurality of consecutive bits from the base operand is a LSB of a second plurality of consecutive bits from the base operand; and receiving a first plurality of consecutive bits from an offset operand, wherein a MSB of the first plurality of consecutive bits from the offset operand is a LSB of a second plurality of consecutive bits from the offset operand. The method includes summing the first plurality of consecutive bits from the base operand with the first plurality of consecutive bits from the offset operand to generate a sum value; and allowing access to one of a plurality of memory arrays and disabling access to the remainder of the plurality of memory arrays when a lesser significant bit to a MSB of the sum value equals zero. | 09-18-2014 |
20150061097 | EDGE COUPLING OF SEMICONDUCTOR DIES - Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together. | 03-05-2015 |