Patent application number | Description | Published |
20090185323 | OVERHEAT PROTECTION CIRCUIT - In order to provide an overheat protection circuit having a small mounting area, the overheat protection circuit includes: a resistor bridge circuit which includes: a plurality of resistors each having a temperature coefficient; an input terminal; and an output terminal; and a comparator circuit connected to the output terminal and the input terminal of the resistor bridge circuit. Parts are each provided in the vicinity of one of the plurality of resistors each having the temperature coefficient, and the comparator circuit outputs an overheat detection signal when a temperature of one of the parts is equal to or higher than an overheat detection temperature. With this structure, a large number of parts can be protected from overheating by a minimum number of overheat protection circuits. Therefore, a circuit scale becomes smaller, and hence a cost for overheat protection becomes lower. | 07-23-2009 |
20100194343 | BATTERY STATE MONITORING CIRCUIT AND BATTERY DEVICE - Provided are a battery state monitoring circuit and a battery device which are capable of inhibiting discharge without enabling an overdischarge cell balance function when an overcurrent detection circuit detects a discharge overcurrent, without the need for an additional terminal of the battery state monitoring circuit. A detection signal of the overcurrent detection circuit is input to each of a communication terminal for overdischarge signal and a communication terminal for overcharge signal included in the battery state monitoring circuit provided on a side of the overcurrent detection circuit. An overdischarge cell balance circuit outputs a cell balance signal when an overdischarge detection signal indicates an overdischarge non-detected state, an overdischarge signal indicates an overdischarge detected state, and an overcharge signal indicates an overcharge non-detected state. | 08-05-2010 |
20110050172 | CHARGE/DISCHARGE CONTROL CIRCUIT AND CHARGING TYPE POWER SUPPLY DEVICE - Provided are a charge/discharge control circuit and a charging type power supply device which include an intermediate terminal disconnection detection circuit having low current consumption. In the charge/discharge control circuit, a constant current circuit serving as an intermediate terminal disconnection detection circuit is provided to a terminal to which secondary batteries are connected, and includes a depletion type metal oxide semiconductor (MOS) transistor and a resistor connected between a gate terminal and a source terminal of the depletion type MOS transistor. | 03-03-2011 |
20110050176 | BATTERY STATE MONITORING CIRCUIT AND BATTERY DEVICE - Provided are a battery state monitoring circuit and a battery device that are capable of reliably controlling charge by a charger even if a voltage of a secondary battery drops to around 0 V. In the battery device provided with the battery state monitoring circuit, respective gate voltages of a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor, which together form a voltage detection circuit for detecting a voltage of around 0 V of the secondary battery, are applied by a voltage dividing resistor circuit that is connected across terminals of the secondary battery. | 03-03-2011 |
Patent application number | Description | Published |
20120025293 | SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING GATE AND A CONTROL GATE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device having a memory cells and word lines is provided. The memory cells are formed in a semiconductor layer and arranged in matrix. Each of the memory cells has a floating gate and a control gate. Each plurality of the memory cells is connected in series in a row direction. Each of the word lines is connected to each plurality of the control gates in a column direction. First and second intervals are provided for the memory cells alternately in the column direction. The second interval is larger than the first interval. | 02-02-2012 |
20140001532 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME | 01-02-2014 |
20140070305 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a non-volatile memory device includes a memory cell including a semiconductor layer, a charge storage layer provided on the semiconductor layer, and a first insulating film provided between the semiconductor layer and the charge storage layer. The device also includes a first conductive layer provided on the charge storage layer, a second conductive layer provided between the charge storage layer and the first conductive layer, a second insulating film provided between the charge storage layer and the second conductive layer, and a third insulating film provided between the first conductive layer and the second conductive layer. | 03-13-2014 |
20140071759 | NONVOLATILE MEMORY DEVICE - According to an embodiment, a nonvolatile memory device includes a plurality of memory cell strings disposed in parallel in a first direction, a bit line and a first contact plug. Each of the memory cell strings extends in a second direction orthogonal to the first direction and includes a plurality of memory cells disposed in parallel in the second direction. The bit line is shared by two adjacent memory cell strings of the memory cell strings, and the first contact plug is connected to the bit line and one of the two adjacent memory cell strings. The bit line includes a first transistor section controlling a current flowing in the one of the adjacent memory cell strings. | 03-13-2014 |
Patent application number | Description | Published |
20120069669 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING AND MANUFACTURING THE SAME - A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data retention and the second memory cell is used for adjustment of a threshold voltage of the first memory cell. The programming circuit is configured to program the first memory cell by applying voltage to the second memory cell to control the threshold voltage of the first memory cell to be higher than a first threshold voltage. | 03-22-2012 |
20130207175 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device including a first transistor comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer; a second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; and a third transistor comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side taken along a length direction of the second and the third gate electrodes, the lower electrodes of the second and the third gate electrodes including a lower silicide portion in which at least the first side of the lower electrodes are partially silicided. | 08-15-2013 |
20140264537 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device including a memory cell region including a memory cell having a charge storing layer above a gate insulating film and a control electrode above the charge storing layer via an interelectrode insulating film; and a peripheral circuit region including a peripheral element having a first polysilicon and a first insulating film above the first polysilicon; wherein the charge storing layer includes a polysilicon doped with P-type impurity including a first upper region contacting the interelectrode insulating film and having a first doped layer doped with carbon or nitrogen, and at least a portion of a region below the first doped layer is neither doped with carbon nor nitrogen, and wherein the first polysilicon includes a second upper region contacting the first insulating film and having a second doped layer doped with carbon or nitrogen, the first and the second doped layers having equal thickness. | 09-18-2014 |
20150060995 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - Nonvolatile semiconductor storage device provided with first to fourth memory-cell unit each including a first select transistor, a second select transistor series connected to the first select transistor, a third select transistor, and memory-cell transistors series connected between the first and the second select transistors and the third select transistor. The memory-cell transistors have a stack structure including a charge storing layer and a control electrode above the charge storing layer via an insulating film. The first to third select transistors each has a stack structure substantially identical to the aforementioned stack structure. Threshold voltages of the first select transistors in the first and the fourth memory-cell unit and the second transistors in the second and third memory-cell unit differ from the threshold voltages of the second select transistors in the first and the fourth memory-cell unit and the first select transistors in the second and third memory-cell unit. | 03-05-2015 |
20150076578 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device is provided with a memory-cell region; a peripheral-circuit region disposed adjacent to the memory-cell region a first memory-cell unit disposed in a first layer located in the memory-cell region; a second memory-cell unit disposed in a k-th layer of the memory-cell region where k is an integer equal to or greater than 2, the second memory-cell unit having an element region extending in a first direction and having a first width in a second direction crossing the first direction; and a peripheral-circuit element disposed in the first layer located in the peripheral-circuit region. Two or more dummy element each having a second width 2n+1 times greater than the first width in the second direction are disposed in the k-th layer located in the peripheral-circuit region where n is an integer equal to or greater than 0. | 03-19-2015 |
Patent application number | Description | Published |
20120069678 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR DRIVING THE SAME - A storage device according to one embodiment includes memory cells which are connected in series in a first direction and are arranged in a matrix by the arranged series connections, and word lines which connect control gates of the memory cells in a second direction perpendicular to the first direction, in which a first interval and a second interval wider than that are alternately repeated for intervals in the second direction between the memory cells. The storage device according to the embodiment comprises a drive unit for writing data in a first cell, then writing data in a second cell which is connected to the same word line as the first cell and is spaced at the first interval in the second direction, then reading the data in the second cell, and reading the data in the first cell with correction based on the read value of the second cell. | 03-22-2012 |
20120126303 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode. | 05-24-2012 |
20120126306 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a memory cell includes a charge storage layer. A first air gap is provided between charge storage layers adjacent in a word line direction. A second air gap is provided between charge storage layers adjacent in a bit line direction. | 05-24-2012 |
20140029339 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ITS USE - A nonvolatile semiconductor memory device comprises multiple cell units that are arranged in the form of a matrix in the memory cell region, a bit line that is connected to the drain of one side of the selector gate transistor of each of the cell units and that is arranged in an extending direction of the multiple cell units, a source line that is connected to the source of the other side of the selector gate transistor of each of the cell units and that is arranged at right angle to the multiple cell units, and a bit line charge-discharge transistor that charges and discharges the bit line and that is arranged adjacent to the contact connected to the bit line on the region of drain side of at least one of the selector gate transistors of the multiple cell units. | 01-30-2014 |
20140043909 | WRITING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a writing method. The method includes setting potentials of a plurality of word lines to a first potential. The first potential is a potential to allow memory cells corresponding to a selective bit line to be in on state. The method also includes setting potentials of non-adjacent word lines to a second potential while maintaining potentials of adjacent word lines at a potential which allows the memory cells corresponding to the selective bit line to be in on state and setting a potential of a selective word line to a third potential. The second potential is a potential which is determined so as to allow the memory cells corresponding to the selective bit line to be in off state. The third potential is a potential where data is written in the selective memory cell corresponding to the selective bit line. | 02-13-2014 |
20140043917 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, there is provided a non-volatile semiconductor storage device including a memory cell and a control unit. The memory cell has a gate electrode including a control gate and a charge storage region on a semiconductor substrate and has a channel region under the gate electrode in the semiconductor substrate. The control unit, during an erase operation where electric charges written in the charge storage region are extracted to the channel region, periodically varies a voltage which is to be applied between the control gate and the channel region. | 02-13-2014 |
20140332816 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating film formed on a memory cell region of the semiconductor substrate, a first polysilicon layer formed on the first insulating film, and memory cell transistors formed on the first polysilicon layer, each including a charge storage layer, an inter-electrode insulating film and a control gate electrode. The semiconductor device further includes a laminated structure formed on a peripheral circuit region of the semiconductor substrate that includes a second insulating film, a second polysilicon layer, a third insulating film, a third polysilicon layer, a fourth insulating film formed from the same material as a material of the inter-electrode insulating film, and a first electrode formed from the same material as a material of the control gate electrode. The third polysilicon layer, the fourth insulating film, and the first electrode are arranged in the peripheral circuit region to form a capacitance element. | 11-13-2014 |