Patent application number | Description | Published |
20080231779 | Display substrate and display apparatus having the same - A display substrate includes a pixel layer, a color filter layer and a pixel electrode. The pixel layer includes a first storage electrode, a second storage electrode and a third storage electrode respectively associated with a red pixel, a green pixel and a blue pixel. At least one of the first, second and third storage electrodes has a different area from a remainder of the storage electrodes. The color filter layer includes a red color filter, a green color filter and a blue color filter formed on the pixel layer. The red, green and blue color filters respectively correspond to the red pixel, the green pixel and the blue pixel. Pixel electrodes are formed on the color filter layer. The pixel electrodes correspond to the red, green and blue pixels. | 09-25-2008 |
20090121228 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed. | 05-14-2009 |
20090130789 | SIGNAL LINE FOR DISPLAY DEVICE AND THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SIGNAL LINE - A thin film transistor (TFT) array panel with signal lines that have low resistivity is presented. The TFT array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap, and a pixel electrode connected to the drain electrode. In one embodiment, at least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor. | 05-21-2009 |
20100261322 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed. | 10-14-2010 |