Patent application number | Description | Published |
20080277802 | Flip-chip semiconductor package and package substrate applicable thereto - A flip-chip semiconductor package structure and a package substrate applicable thereto are disclosed. The package substrate includes a body having at least a chip-attach area disposed thereon; a plurality of solder pads disposed in the chip-attach area and arranged at different intervals; and a fluid-disturbing portion disposed in the chip-attach area at a position where the solder pads are loosely arranged. A flip-chip semiconductor chip is mounted on the solder pads via conductive bumps and an underfill material is filled between the package substrate and the flip-chip semiconductor chip, the underfill material encapsulating the conductive bumps and the fluid-disturbing portion. By protrudingly disposing the fluid-disturbing portion at a position where the conductive bumps are loosely arranged, that is, the conductive bumps having bigger intervals therebetween, gap between the package substrate and the flip-chip semiconductor chip can be reduced so as to increase capillary attraction generated by capillary phenomenon, thereby balancing flow rate of the underfill material between the conductive bumps that are arranged at different intervals and thus avoiding problems of void formation, subsequent popcorn effect or delamination as encountered in the prior art. | 11-13-2008 |
20130299968 | SEMICONDUCTOR PACKAGE AND A SUBSTRATE FOR PACKAGING - A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination. | 11-14-2013 |
20130334684 | SUBSTRATE STRUCTURE AND PACKAGE STRUCTURE - A substrate structure is provided, including a substrate body and a plurality of traces formed on a surface of the substrate body. At least one of the traces has an electrical contact formed in a groove thereof for electrically connecting an external element, thereby meeting the demands of fine line/fine pitch and miniaturization and improving the product yield. | 12-19-2013 |
20130341806 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE USING THE SAME - A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an electrical contact for connecting to an external element and the electrical contact is narrower in width than the circuit, thereby meeting the requirements of fine line/fine pitch and miniaturization, improving the product yield and reducing the fabrication cost. | 12-26-2013 |
20140179067 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip. | 06-26-2014 |
20150014848 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield. | 01-15-2015 |
20150069605 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF AND SEMICONDUCTOR STRUCTURE - A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer. | 03-12-2015 |
20150235914 | FLIP-CHIP PACKAGING SUBSTRATE, FLIP-CHIP PACKAGE AND FABRICATION METHODS THEREOF - A flip-chip packaging substrate is provided, which includes: a substrate body; a plurality of conductive pads formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having a plurality of openings correspondingly exposing a portion of each of the conductive pads; and a metal layer formed on each of the conductive pads in the openings, wherein the metal layer has a top surface having a lowest point lower than a top surface of the insulating layer, and a thickness ratio of the metal layer to the insulating layer is greater than or equal to 1/4 and less than 1, thereby preventing a solder bridge or short circuit from occurring. | 08-20-2015 |