Patent application number | Description | Published |
20080222587 | Integrated Circuit Cell Library for Multiple Patterning - A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium. | 09-11-2008 |
20090023101 | LITHOGRAPHY TRACK SYSTEMS AND METHODS FOR ELECTRONIC DEVICE MANUFACTURING - The present invention provides systems, methods, and apparatus for processing a lot of substrates in a lithography track system with an integrate metrology sensor. The invention includes performing a coating process on substrates; transferring the substrates to a stepper for alignment and exposure; transferring the substrates to a post-exposure bake chamber for bake; and performing metrology on the substrates in the lithography track system. The invention may further include automatically reworking substrates in an integrated rework chamber within the lithography track system. Numerous other aspects are provided. | 01-22-2009 |
20090023230 | METHODS AND APPARATUS FOR DEPOSITING AN ANTI-REFLECTION COATING - Systems, methods, and apparatus are provided for depositing an anti-reflection film on a substrate. A substrate is transported to a metrology tool. A characteristic of the substrate is measured, via the metrology tool. A recipe for an anti-reflection film is determined, based on the measured characteristic. The substrate is transported from the metrology tool to a process chamber. The recipe is employed to form an anti-reflection film on the substrate within the process chamber. Numerous other aspects are provided. | 01-22-2009 |
20090032898 | Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same - A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo. | 02-05-2009 |
20090032967 | Semiconductor Device with Dynamic Array Section - A semiconductor chip is provided to include one or more distinct but functionally interfaced dynamic array sections. Each dynamic array section follows a dynamic array architecture that requires conductive features to be linearly defined along a virtual grate in each of a plurality of levels of the semiconductor chip. Each virtual grate is perpendicular to another virtual grate that is either a level above or a level below. Each virtual grate is defined by a framework of parallel lines spaced at a constant pitch. Some of the lines in the virtual grate are occupied by multiple conductive features. A substantially uniform gap can be maintained between proximate ends of adjacent conductive features that occupy a common line in the virtual grate. The substantially uniform gap between the proximate ends of adjacent conductive features can be maintained within each line in the virtual grate that is occupied by multiple conductive features. | 02-05-2009 |
20090037864 | Methods for Designing Semiconductor Device with Dynamic Array Section - A method is provided for designing a semiconductor chip having one or more functionally interfaced dynamic array sections. A virtual grate is laid out for conductive features used to define a gate electrode level of a dynamic array section. The virtual grate is defined by a framework of parallel lines defined at a substantially constant pitch. One or more conductive features are arranged along every line of the virtual grate. For each line of the virtual grate, a gap is defined between proximate ends of each pair of adjacent conductive features which are arranged along a common line of the virtual grate. Each gap is defined to maintain a substantially consistent separation between proximate ends of conductive features. Each conductive feature is defined to be devoid of a substantial change in direction, such that the conductive features remain substantially aligned to the framework of parallel lines of the virtual grate. | 02-05-2009 |
20090066358 | METHODS AND APPARATUS FOR DETECTING DEFECTS IN INTERCONNECT STRUCTURES - In some aspects, a method is provided for detecting a void in a test structure that comprises (a) measuring a resistance of the test structure; (b) applying a stress to the test structure at increasing levels until at least one of: (i) the measured resistance of the test structure exceeds a predetermined resistance threshold; and (ii) the stress level reaches a predetermined stress maximum; (c) detecting a void if the measured resistance of the test structure exceeds the predetermined resistance threshold; and (d) determining that the test structure is void free if the stress level reaches the predetermined stress maximum without the measured resistance of the test structure exceeding the predetermined resistance threshold. Numerous other aspects are provided. | 03-12-2009 |
20090100396 | Methods and Systems for Process Compensation Technique Acceleration - Selected cells in a semiconductor chip layout are replaced with corresponding PCT pre-processed cells. Each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments. Following replacement of the selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, a chip-wide PCT processing operation is performed on the semiconductor chip layout for a given chip level. The presence of the PCT pre-processed cells in the semiconductor chip layout serves to accelerate the chip-wide PCT processing of the semiconductor chip layout. The chip-wide PCT processed semiconductor layout for the given chip level is recorded on a persistent storage medium. | 04-16-2009 |
20090108360 | METHODS, STRUCTURES AND DESIGNS FOR SELF-ALIGNING LOCAL INTERCONNECTS USED IN INTEGRATED CIRCUITS - Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates. | 04-30-2009 |
20090127636 | Diffusion Variability Control and Transistor Device Sizing Using Threshold Voltage Implant - A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is defined within a portion of the diffusion region so as to transform the operable transistor threshold voltage of the diffusion region portion into an inoperably high transistor threshold voltage. A gate electrode is defined to extend over both the diffusion region and the implant region. A first portion of the gate electrode defined over the diffusion region forms a first transistor segment having the operable transistor threshold voltage. A second portion of the gate electrode defined over the implant region forms a second transistor segment having the inoperably high transistor threshold voltage. Therefore, a boundary of the implant region defines a boundary of the operable first transistor segment. | 05-21-2009 |
20090152734 | Super-Self-Aligned Contacts and Method for Making the Same - A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact. | 06-18-2009 |
20090294981 | Methods for Defining and Using Co-Optimized Nanopatterns for Integrated Circuit Design and Apparatus Implementing Same - A set of layout nanopatterns is defined. Each layout nanopattern is defined by relative placements of a particular type of layout feature within a lithographic window of influence. A design space is defined as a set of layout parameters and corresponding value ranges that affect manufacturability of a layout. Layouts are created for the set of layout nanopatterns such that the created layouts cover the design space. The layouts for the set of layout nanopatterns are then optimized for manufacturability. A point in the design space is selected where the set of layout nanopatterns are co-optimized for manufacturability. A circuit layout is created based on the selected point in design space using the corresponding set of co-optimized layout nanopatterns. The optimized layouts for the set of layout nanopatterns and the associated circuit layout can be recorded in a digital format on a computer readable storage medium. | 12-03-2009 |
20100031211 | Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication - Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures. | 02-04-2010 |
20100306719 | Integrated Circuit Cell Library with Cell-Level Process Compensation Technique (PCT) Application and Associated Methods - A layout of cells is generated to satisfy a netlist of an integrated circuit. Cell-level process compensation technique (PCT) processing is performed on a number of levels of one or more cells in the layout to generate a PCT processed version of the one more cells in the layout. An as-fabricated aerial image of each PCT processed cell level is generated to facilitate evaluation of PCT processing adequacy. Cell-level circuit extraction is performed on the PCT processed version of each cell using the generated as-fabricated aerial images. The cell-level PCT processing and cell-level circuit extraction are performed before placing and routing of the layout on a chip. The PCT processed version of the one or more cells and corresponding as-fabricated aerial images are stored in a cell library. | 12-02-2010 |
20110108890 | Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos - An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction. Some of the three or more linear conductive segments within the gate electrode levels of the adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the adjoining pair of dynamic array sections. Each of these end-to-end spacings is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of the co-aligned linear conductive segments. | 05-12-2011 |
20110108891 | Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos - An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending in the first direction. At least one of the linear conductive segments within the gate electrode level of a given dynamic array section is a non-gate linear conductive segment that does not form a gate electrode of a transistor. The non-gate linear conductive segment of either of the adjoining pair of dynamic array sections spans the co-located portion of outer peripheral boundary segment toward the other of the adjoining pair of dynamic array sections, and is contained within gate electrode level manufacturing assurance halo portions of the adjoining pair of dynamic array sections. | 05-12-2011 |
20110161909 | Methods for Designing Semiconductor Device with Dynamic Array Section - A method is provided for designing an integrated circuit device. The method includes placing four transistors of a first transistor type and four transistors of a second transistor type within a gate electrode level. Each of the transistors includes a respective linear-shaped gate electrode segment positioned to extend lengthwise in a first direction. The transistors of the first and second transistor types are placed according to a substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction. A first linear conductive segment is placed to electrically connect the gate electrodes of the first transistors of the first and second transistor types. A second linear conductive segment is placed to electrically connect the gate electrodes of the fourth transistors of the first and second transistor types. A third linear conductive segment is placed beside either the first or second linear conductive segment. | 06-30-2011 |
20110175144 | Integrated Circuit Device Including Dynamic Array Section with Gate Level Having Linear Conductive Features on at Least Three Side-by-Side Lines and Uniform Line End Spacings - An integrated circuit device includes a dynamic array section that includes a gate electrode level region that has linear conductive features defined in accordance with a gate level virtual grate. Each of at least three consecutively positioned virtual lines of the gate level virtual grate has at least one linear conductive feature defined thereon. A first virtual line of the at least three virtual lines has two linear conductive segments defined thereon and separated by a first end-to-end spacing. A second virtual line of the at least three virtual lines has another two linear conductive segments defined thereon and separated by a second end-to-end spacing. A size of the first end-to-end spacing as measured along the first virtual line is substantially equal to a size of the second end-to-end spacing as measured along the second virtual line. | 07-21-2011 |
20110278681 | Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits - An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures. | 11-17-2011 |
20120118854 | Methods for linewidth modification and apparatus implementing the same - A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. The layer of the second material is etched so as to leave a filament of the second material on each sidewall of the linear-shaped core structure, and so as to remove the second material from the underlying material. The linear-shaped core structure of the first material is removed so as to leave each filament of the second material on the underlying material. Each filament of the second material provides a mask for etching the underlying material. Each filament of the second material can be selectively etched further to adjust its size, and to correspondingly adjust a size of a feature to be formed in the underlying material. | 05-17-2012 |
20120144360 | Scalable Meta-Data Objects - A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium. | 06-07-2012 |
20130126978 | CIRCUITS WITH LINEAR FINFET STRUCTURES - A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin. | 05-23-2013 |
20130130511 | Coarse Grid Design Methods and Structures - A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate. | 05-23-2013 |
20130161760 | Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings - An integrated circuit includes a first gate electrode feature of a first gate electrode track that forms a first n-channel transistor as it crosses an n-diffusion region, and a second gate electrode feature of the first gate electrode track that forms a first p-channel transistor as it crosses a p-diffusion region. The first and second gate electrode features of the first gate electrode track are separated by a first end-to-end spacing. The integrated circuit includes a first gate electrode feature of a second gate electrode track that forms a second n-channel transistor as it crosses the n-diffusion region, and a second gate electrode feature of the second gate electrode track that forms a second p-channel transistor as it crosses the p-diffusion region. The first and second gate electrode features of the second gate electrode track are separated by a second end-to-end spacing that is offset from the first end-to-end spacing. | 06-27-2013 |
20130168777 | Integrated Circuit Including Gate Electrode Tracks Forming Gate Electrodes of Different Transistor Types and Linear Shaped Conductor Electrically Connecting Gate Electrodes - An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features. | 07-04-2013 |
20130168778 | Integrated Circuit Including Gate Electrode Tracks That Each Form Gate Electrodes of Different Transistor Types With Intervening Non-Gate-Forming Gate Electrode Track - A first gate electrode track includes a first gate electrode feature forming a first n-channel transistor with a first n-diffusion region and a second gate electrode feature forming a first p-channel transistor with a first p-diffusion region. A second gate electrode track includes a third gate electrode feature forming a second n-channel transistor with a second n-diffusion region and a fourth gate electrode feature forming a second p-channel transistor with a second p-diffusion region. A third gate electrode track is positioned between and parallel to the first and second gate electrode tracks, such that no other gate electrode track is positioned between the third gate electrode track and either of the first or second gate electrode tracks. The third gate electrode track is not interrupted between the first and second gate electrode tracks. The third gate electrode track does not include a gate electrode feature of any transistor. | 07-04-2013 |
20130175639 | Integrated Circuit Including At Least Four Linear-Shaped Conductive Structures Having Extending Portions of Different Length - An integrated circuit includes at least four linear-shaped conductive structures formed to extend lengthwise in a parallel direction to each other and each respectively including a gate electrode portion and an extending portion that extends away from the gate electrode portion. The gate electrode portions of the linear-shaped conductive structures respectively form gate electrodes of different transistors, such that at least one of the linear-shaped conductive structures forms a gate electrode of a transistor of a first transistor type and does not form a gate electrode of any transistor of a second transistor type, and such that at least one of the linear-shaped conductive structures forms a gate electrode of a transistor of the second transistor type and does not form a gate electrode of any transistor of the first transistor type. Extending portions of the at least four linear-shaped conductive structures include at least two different extending portion lengths. | 07-11-2013 |
20130200436 | Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends - A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES. | 08-08-2013 |
20130200462 | Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level - A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES. | 08-08-2013 |
20130207165 | Integrated Circuit Including Gate Electrode Conductive Structures With Different Extension Distances Beyond Contact - An integrated circuit includes four parallel positioned linear-shaped structures each including a gate electrode portion and an extension portion. Gate electrode portions of two of the four linear-shaped structures respectively form gate electrodes of first and second transistors of a first transistor type. Gate electrode portions of two of the four linear-shaped structures respectively form a gate electrodes of first and second transistors of a second transistor type. Four contacting structures are respectively connected to the extension portions of the four linear-shaped structures such that each extension portion has a respective contact-to-end distance. At least two of the contact-to-end distances are different. A fifth linear-shaped structure forms gate electrodes of transistors respectively positioned next to the first transistors of the first and second transistor types. A sixth linear-shaped structure forms gate electrodes of transistors respectively positioned next to the second transistors of the first and second transistor types. | 08-15-2013 |
20130207199 | Finfet Transistor Circuit - A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned. | 08-15-2013 |
20130249013 | Integrated Circuit Including Linear Gate Electrode Structures Having Different Extension Distances Beyond Contact - A first linear-shaped conductive structure (LSCS) forming gate electrodes of both a first p-transistor and a first n-transistor. A second LSCS forming a gate electrode of a second p-transistor and including an extension portion extending away therefrom. A third LSCS forming a gate electrode of a second n-transistor and including an extension portion extending away therefrom. A fourth LSCS forming a gate electrode of a third p-transistor and including an extension portion extending away therefrom. A fifth LSCS forming a gate electrode of a third n-transistor and including an extension portion extending away therefrom. A sixth LSCS forming gate electrodes of both a fourth p-transistor and a fourth n-transistor. Four contact structures respectively contacting the extension portions of the second, third, fourth, and fifth LSCS's, such that at least two of the extension portions extend different distances beyond their contact structure. | 09-26-2013 |
20140030890 | Super-Self-Aligned Contacts and Method for Making the Same - A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact. | 01-30-2014 |
20140167183 | Coarse Grid Design Methods and Structures - A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate. | 06-19-2014 |
20140167185 | Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits - An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures. | 06-19-2014 |
20140175565 | Integrated Circuit Cell Library for Multiple Patterning - A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium. | 06-26-2014 |
20140246733 | Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section - A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing. The second and fourth ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a second end-to-end spacing substantially equal in size to the first end-to-end spacing. | 09-04-2014 |
20140291731 | Semiconductor Chip Including Region Including Linear-Shaped Conductive Structures Forming Gate Electrodes and Having Electrical Connection Areas Arranged Relative to Inner Region Between Transistors of Different Types and Associated Methods - A first linear-shaped conductive structure (LCS) forms gate electrodes (GE's) of a first transistor of a first transistor type and a first transistor of a second transistor type. A second LCS forms a GE of a second transistor of the first transistor type. A third LCS forms a GE of a second transistor of the second transistor type. A fourth LCS forms a GE of a third transistor of the first transistor type. A fifth LCS forms a GE of a third transistor of the second transistor type. A sixth LCS forms a GE of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. The second, third, fourth, and fifth LCS's have respective electrical connection areas arranged relative to the inner region. | 10-02-2014 |
20140380260 | Scalable Meta-Data Objects - A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium. | 12-25-2014 |