Patent application number | Description | Published |
20140262010 | Microwave Bonding Of EVA And Rubber Items - Aspects of the present invention relate to systems and methods for customizing microwave energy distribution within a chamber to accommodate various load characteristics. Aspects of the present invention customized configurations of ports, deflectors, waveguides, conducting rods, and slots to shape and distribute energy. | 09-18-2014 |
20140263290 | Microwave Treatment Of Materials - Microwave energy is used to affix an ethylene-vinyl acetate (“EVA”) item to a rubber item by placing an at least partially cured EVA item in contact with a less than cured rubber item forming a bi-component member. The bi-component member is enclosed in a cavity formed from a material having a first dielectric constant less than or equal to a second dielectric constant of the partially cured EVA item. Microwaves and pressure are applied through the cavity to the at least partially cured EVA item and the less than cured rubber item for a predetermined amount of time to cause the affixing of the portions forming the bi-component member. | 09-18-2014 |
20140263294 | Customized Microwave Energy Distribution Utilizing Slotted Cage - Aspects of the present invention relate to systems and methods for customizing microwave energy distribution within a chamber to accommodate various load characteristics. Aspects of the present invention customized configurations of ports, deflectors, waveguides, conducting rods, and slots to shape and distribute energy. | 09-18-2014 |
20140263295 | Customized Microwaving Energy Distribution Utilizing Slotted Wave Guides - Aspects of the present invention relate to systems and methods for customizing microwave energy distribution within a chamber to accommodate various load characteristics. Aspects of the present invention customized configurations of ports, deflectors, waveguides, conducting rods, and slots to shape and distribute energy. | 09-18-2014 |
20140263296 | Customized Microwave Energy Distribution Utilizing Multiport Chamber - Aspects of the present invention relate to systems and methods for customizing microwave energy distribution within a chamber to accommodate various load characteristics. Aspects of the present invention customized configurations of ports, deflectors, waveguides, conducting rods, and slots to shape and distribute energy. | 09-18-2014 |
Patent application number | Description | Published |
20120104491 | Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells - A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed. | 05-03-2012 |
20120292716 | DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF - A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines. | 11-22-2012 |
20120329274 | METHOD OF FABRICATING A CELL CONTACT AND A DIGIT LINE FOR A SEMICONDUCTOR DEVICE - The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line. | 12-27-2012 |
20130001666 | Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells - A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed. | 01-03-2013 |
20140042548 | DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF - A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines. | 02-13-2014 |
20140159140 | BURIED WORD LINE STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer. | 06-12-2014 |
20140213035 | METHOD OF FORMING BURIED WORD LINE STRUCTURE - A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer. | 07-31-2014 |
20140346652 | BURIED DIGITLINE (BDL) ACCESS DEVICE AND MEMORY ARRAY - A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench. | 11-27-2014 |
20150056810 | METHOD FOR SEMICONDUCTOR CROSS PITCH DOUBLED PATTERNING PROCESS - The present invention provides a method of cross double pitch patterning for forming a contact printing mask. First, a first, a second and a third layer a successively deposited; a photoresist is deposited on the third layer, and then trimmed into a first pre-pattern, on which an oxide layer is deposited. The oxide layer is etched into spacers forming a first pattern that is then etched into the third layer. A second cross pattern is formed the same way on the third layer. Finally the first and second layers are etched with selectivity both patterns. | 02-26-2015 |
Patent application number | Description | Published |
20120299088 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 11-29-2012 |
20130026471 | Circuit Structures, Memory Circuitry, And Methods - A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed. | 01-31-2013 |
20130235642 | Arrays Of Vertically-Oriented Transistors, Memory Arrays Including Vertically-Oriented Transistors, And Memory Cells - An array includes a plurality of vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include an inner data/sense line elevationally inward of the access lines and which interconnect transistors in that column. An outer data/sense line is elevationally outward of the access lines and electrically couples to the inner data/sense line. Other embodiments are disclosed, including memory arrays and memory cells. | 09-12-2013 |
20140017865 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 01-16-2014 |
20140273358 | Circuit Structures, Memory Circuitry, And Methods - A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed. | 09-18-2014 |
20150014766 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 01-15-2015 |
Patent application number | Description | Published |
20140186859 | AUTOFOCUS METHOD FOR IMAGING A BIOLOGICAL SAMPLE AND CARTRIDGE FOR USE THEREIN - A method of automatically focusing a microscope on a specimen is carried out by capturing an image from each of a plurality of focal planes in or on said specimen, calculating a focus score for each of said images, selecting the focal plane corresponding to the image having the best focus score, and then repositioning said specimen relative to said microscope so that said microscope is focused on said selected focal plane, the method includes a plurality of exogenous targets in or on said specimen, which aids in focusing in the event particular objects of interest, such as cells/pathogens that may or may not be in the sample, are not present, or are present in low numbers. Automated microscopes and microscope cartridges useful in such methods are also described, along with methods of detecting pathogens in biological samples. | 07-03-2014 |
20140233098 | DIAGNOSTIC APPARATUS - An automated microscope apparatus comprises an outer housing having an external wall; optionally but preferably an internal wall in the housing configured to form a first compartment and a separate second compartment in the outer housing; a microscope assembly in the housing (preferably in the first compartment); a microprocessor in the housing (preferably in the second compartment), and (optionally but preferably) a heat sink mounted on the housing external wall, preferably adjacent the second compartment, with the microprocessor thermally coupled to said heat sink and operatively associated with the microscope assembly. Systems and methods employing the same are also described, along with component parts thereof. | 08-21-2014 |
20140315283 | SAMPLE CARTRIDGE AND SAMPLE STAGE - A sample cartridge ( | 10-23-2014 |
20140363882 | RAPID DETECTION OF ANALYTES IN LIQUID SAMPLES - A device for detecting at least one analyte in a liquid sample generally comprises (i) a support having a chamber for receiving a biological fluid (e.g., milk) therein, wherein said chamber is an elongate chamber having a length axis; (ii) a (stationary or movable) carrier (in some embodiments in the form of an end cap, or connected to an end cap; in other embodiments in the form of an agitator in said elongate chamber). | 12-11-2014 |
20150037835 | SYSTEM AND METHOD FOR AUTOMATED DIAGNOSIS - An automated microscope apparatus comprises an outer housing having an external wall; optionally but preferably an internal wall in the housing configured to form a first compartment and a separate second compartment in the outer housing; a microscope assembly in the housing (preferably in the first compartment); a microprocessor in the housing (preferably in the second compartment), and (optionally but preferably) a heat sink mounted on the housing external wall, preferably adjacent the second compartment, with the microprocessor thermally coupled to said heat sink and operatively associated with the microscope assembly. Systems and methods employing the same are also described, along with component parts thereof. | 02-05-2015 |