Patent application number | Description | Published |
20140115280 | FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER - A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address. | 04-24-2014 |
20140143471 | FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER - A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address. | 05-22-2014 |
20140143500 | FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER - A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address. | 05-22-2014 |
20140201454 | Methods And Systems For Pushing Dirty Linefill Buffer Contents To External Bus Upon Linefill Request Failures - Methods and systems are disclosed for recovering dirty linefill buffer data upon linefill request failures. When a linefill request failure occurs and the linefill buffer has been marked as dirty, such as due to a system bus failure, the contents of the linefill buffer are pushed back to the system bus. The dirty data within the linefill buffer can then be used to update the external memory. The disclosed embodiments are useful for a wide variety of applications, including those requiring low data failure rates. | 07-17-2014 |
Patent application number | Description | Published |
20090177845 | SNOOP REQUEST MANAGEMENT IN A DATA PROCESSING SYSTEM - Snoop requests are managed in a data processing system having a cache coupled to a processor that provides access addresses to the cache. Snoop queue circuitry provides snoop addresses to the cache via an arbiter. The snoop queue circuitry has a snoop request queue for storing a plurality of entries. Each entry of the snoop request queue that corresponds to a snoop request includes a snoop address and a corresponding status indicator. The corresponding status indicator indicates whether the snoop request has zero or more collapsed snoop requests having a common snoop address which have been merged to form the snoop request. The status indicator is used for debug and by fullness management logic to manage the capacity of the snoop request queue. A general collapsed status signal is generated to indicate whenever any snoop queue entry collapsing occurs. | 07-09-2009 |
20090300294 | UTILIZATION OF A STORE BUFFER FOR ERROR RECOVERY ON A STORE ALLOCATION CACHE MISS - A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry are written to the cache in response to error free receipt. A second buffer circuit coupled to the cache has one or more entries for storing store requests. Each entry has an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit. Based upon error free receipt of the one or more data words, the associated control bit is set to a value that invalidates the entry in the second buffer circuit based upon the error determination. | 12-03-2009 |
20100057998 | SNOOP REQUEST ARBITRATION IN A DATA PROCESSING SYSTEM - A snoop look-up operation is performed in a system having a cache and a first processor. The processor generates requests to the cache for data. A snoop queue is loaded with snoop requests. Fullness of the snoop queue is a measure of how many snoop requests are in the snoop queue. A snoop look-up operation is performed in the cache if the fullness of the snoop queue exceeds the threshold. The snoop look-up operation is based on a snoop request from the snoop queue corresponding to an entry in the snoop queue. If the fullness of the snoop queue does not exceed the threshold, waiting to perform a snoop look-up operation until an idle access request cycle from the processor to the cache occurs and performing the snoop look-up operation in the cache upon the idle access request cycle from the processor. | 03-04-2010 |
20100058000 | SNOOP REQUEST ARBITRATION IN A DATA PROCESSING SYSTEM - A snoop look-up operation is performed in a system having a first cache and a first processor. The first processor generates access requests to the first cache for data. Snoop look-up operations are performed in the cache. The snoop look-up operations are based on snoop requests from a snoop queue. The snoop requests correspond to entries in the snoop queue. An access request from the first processor is performed in response to a consecutive number of snoop look-up operations exceeding a first limit. This is useful in avoiding having no processor operations while performing snoop look-up operations. Similarly, consecutive access requests can be counted and if a second limit is exceeded, a snoop look-up operation can be performed. | 03-04-2010 |
20100064206 | ERROR DETECTION SCHEMES FOR A CACHE IN A DATA PROCESSING SYSTEM - A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines. | 03-11-2010 |