Patent application number | Description | Published |
20080222464 | Structure for System for and Method of Performing High Speed Memory Diagnostics Via Built-In-Self-Test - A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester. | 09-11-2008 |
20090055696 | MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) - Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock. | 02-26-2009 |
20090114913 | TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES - A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C | 05-07-2009 |
20090180584 | DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA - The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register. | 07-16-2009 |
20120221910 | MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) - Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock. | 08-30-2012 |
20120262197 | TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES - A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer. | 10-18-2012 |
20120264241 | TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES - A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer. | 10-18-2012 |
Patent application number | Description | Published |
20120031609 | Low Friction Wireline Standoff - The low friction wireline standoff improves wireline cable performance during borehole logging operations. The use of low friction wireline standoffs ameliorates the effects of wireline cable differential sticking, wireline cable key-seating, and high wireline cable drags, by reducing or eliminating contact of the wireline cable with the borehole wall during the logging operation. The low friction wireline standoff comprises external wheels mounted on two finned half shells that clamp onto the wireline with precision cable inserts which are manufactured to fit a wide range of logging cables. The wheels reduce the cable drag down-hole resulting in lower surface logging tensions, aiding conveyance in deep and deviated wells. | 02-09-2012 |
20140238659 | Articulated Wireline Hole Finder - The articulated wireline hole finder is a modular device which attaches to the bottom of a wireline logging tool-string to aid conveyance down irregular shaped and/or deviated boreholes which possess features such as ledges, washouts, and contractions, that might otherwise terminate full descent of the tool-string to the bottom of the borehole and thereby compromise the wireline data acquisition objectives. Elements of the articulated wireline hole finder may include a low friction roller nose assembly and spacer sub, an articulated spring joint, that transfers tool-string weight and directs lateral movement of the roller nose towards hole center, and a pair of five arm centralizers that possess a wide dynamic range. | 08-28-2014 |
20140367169 | Mud Sensing Hole Finder - A mud sensing hole finder comprising: a front steering wheel assembly, a rear wheel assembly, a sensor package, a corrosion package, a ported housing, and a tapered spring joint; wherein the mud sensing hole finder is capable of attachment to a wireline logging tool-string. | 12-18-2014 |
Patent application number | Description | Published |
20100048474 | METHOD OF TREATING OR PREVENTING TISSUE DETERIORATION, INJURY OR DAMAGE DUE TO PERIODONTAL DISEASE OR DISEASE OF ORAL MUCOSA, AND/OR DOWNREGULATING NF-KAPPABETA OR SUPRESSING NF-KAPPABETA-MEDIATED ACTIONS - A method of treatment for treating, at least partly preventing, inhibiting or reducing tissue deterioration, injury or damage due to a periodontal disease or disease of oral mucosa, or for restoring tissue adversely affected by the disease, in a subject, and/or for downregulating NF-kappaB or suppressing NF-kappaB mediated action in a body, organ, tissue or cell, includes administering to a subject, body, organ, tissue or cell an effective amount of a composition including a peptide agent including at least one of Thymosin beta 4 (Tβ4), an isoform of Tβ4, an N-terminal fragment of Tβ4, a C-terminal fragment of Tβ4, Tβ4 sulfoxide, an LKKTET peptide or conservative variant thereof, an LKKTNT peptide or conservative variant thereof, a KLKKTET peptide or conservative variant thereof, an LKKTETQ peptide or conservative variant thereof, Tβ4 | 02-25-2010 |