Patent application number | Description | Published |
20080212361 | NONVOLATILE NANOTUBE DIODES AND NONVOLATILE NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING SAME - Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell. | 09-04-2008 |
20090052246 | NON-VOLATILE SHADOW LATCH USING A NANOTUBE SWITCH - A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device. | 02-26-2009 |
20090154218 | MEMORY ARRAYS USING NANOTUBE ARTICLES WITH REPROGRAMMABLE RESISTANCE - A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell. | 06-18-2009 |
20090173964 | METHOD OF FORMING A CARBON NANOTUBE-BASED CONTACT TO SEMICONDUCTOR - Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided. | 07-09-2009 |
20090243102 | METHOD OF ALIGNING DEPOSITED NANOTUBES ONTO AN ETCHED FEATURE USING A SPACER - A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature. | 10-01-2009 |
20100012925 | HYBRID CARBON NANOTUBE FET (CNFET)-FET STATIC RAM (SRAM) AND METHOD OF MAKING SAME - Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET. | 01-21-2010 |
20100327247 | METHOD AND SYSTEM OF USING NANOTUBE FABRICS AS JOULE HEATING ELEMENTS FOR MEMORIES AND OTHER APPLICATIONS - Methods and systems of using nanotube elements as joule heating elements for memories and other applications. Under one aspect, a method includes providing an electrical stimulus, regulated by a drive circuit, through a nanotube element in order to heat an adjacent article. Further, a detection circuit electrically gauges the state of the article. The article heated by the nanotube element is, in preferred embodiments, a phase changing material, hi memory applications, the invention may be used as a small-scale CRAM capable of employing small amounts of current to induce rapid, large temperature changes in a chalcogenide material. Under various embodiments of the disclosed invention, the nanotube element is composed of a non-woven nanotube fabric which is either suspended from supports and positioned adjacent to the phase change material or is disposed on a substrate and in direct contact with the phase change material. A plurality of designs using various geometric orientations of nanotube fabrics, phase change materials, and drive and detection circuitry is disclosed. Additionally, methods of fabricating nanotube heat emitters are disclosed. | 12-30-2010 |
20110044091 | TWO-TERMINAL NANOTUBE DEVICES AND SYSTEMS AND METHODS OF MAKING SAME - A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device. | 02-24-2011 |
20110220859 | Two-Terminal Nanotube Devices And Systems And Methods Of Making Same - A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device. | 09-15-2011 |