Patent application number | Description | Published |
20090313445 | System and Method for Improving Memory Locality of Virtual Machines - A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to these pages becomes local as soon as possible. Various heuristics are described to enable different implementations for different situations or scenarios. | 12-17-2009 |
20120017027 | METHOD FOR IMPROVING SAVE AND RESTORE PERFORMANCE IN VIRTUAL MACHINE SYSTEMS - Page data of a virtual machine is represented for efficient save and restore operations. One form of representation applies to each page with an easily identifiable pattern. The page is described, saved, and restored in terms of metadata reflective of the pattern rather than a complete page of data reflecting the pattern. During a save or restore operation, however, the metadata of the page is represented, but not the page data. Another form of representation applies to each page sharing a canonical instance of a complex pattern that is instantiated in memory during execution, and explicitly saved and restored. Each page sharing the canonical page is saved and restored as a metadata reference, without the need to actually save redundant copies of the page data. | 01-19-2012 |
20120030407 | SYSTEM AND METHOD FOR IMPROVING MEMORY LOCALITY OF VIRTUAL MACHINES - A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to these pages becomes local as soon as possible. Various heuristics are described to enable different implementations for different situations or scenarios. | 02-02-2012 |
20120117299 | EFFICIENT ONLINE CONSTRUCTION OF MISS RATE CURVES - Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced. | 05-10-2012 |
20130067135 | SYSTEM AND METHOD FOR IMPROVING MEMORY LOCALITY OF VIRTUAL MACHINES - A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to these pages becomes local as soon as possible. Various heuristics are described to enable different implementations for different situations or scenarios. | 03-14-2013 |
20130346613 | SCHEDULING A PROCESSOR TO SUPPORT EFFICIENT MIGRATION OF A VIRTUAL MACHINE - A virtualized computer system implements a process to migrate a virtual machine (VM) from a source host to a destination host. During this process, a processing unit at the source host, which is executing instructions of the VM, is scheduled so that the rate of modification of guest physical memory pages is reduced. The determination of when to schedule the processing unit in this manner may be made based on a current rate of modification of the pages, a transmission rate of guest physical memory pages from the source host to the destination host, or a prior VM migration performance. | 12-26-2013 |
20140189248 | EFFICIENT ONLINE CONSTRUCTION OF MISS RATE CURVES - Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced. | 07-03-2014 |
20140258670 | SYSTEM AND METHOD FOR EFFICIENT SWAP SPACE ALLOCATION IN A VIRTUALIZED ENVIRONMENT - A technique for efficient swap space management creates a swap reservation file using thick provisioning to accommodate a maximum amount of memory reclamation from a set of one or more associated virtual machines (VMs). A VM swap file is created for each VM using thin provisioning. When a new block is needed to accommodate page swaps to a given VM swap file, a block is removed from the swap reservation file and a block is added to the VM swap file, thereby maintaining a net zero difference in overall swap storage. The removed block and the added block may be the same storage block if a block move operation is supported by a file system implementing the swap reservation file and VM swap files. The technique also accommodates swap space management of resource pools. | 09-11-2014 |
20150052287 | NUMA Scheduling Using Inter-vCPU Memory Access Estimation - In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality. | 02-19-2015 |
20150095576 | CONSISTENT AND EFFICIENT MIRRORING OF NONVOLATILE MEMORY STATE IN VIRTUALIZED ENVIRONMENTS - Updates to nonvolatile memory pages are mirrored so that certain features of a computer system, such as live migration of applications, fault tolerance, and high availability, will be available even when nonvolatile memory is local to the computer system. Mirroring may be carried out when a cache flush instruction is executed to flush contents of the cache into nonvolatile memory. In addition, mirroring may be carried out asynchronously with respect to execution of the cache flush instruction by retrieving content that is to be mirrored from the nonvolatile memory using memory addresses of the nonvolatile memory corresponding to target memory addresses of the cache flush instruction. | 04-02-2015 |
20150095585 | CONSISTENT AND EFFICIENT MIRRORING OF NONVOLATILE MEMORY STATE IN VIRTUALIZED ENVIRONMENTS - Updates to nonvolatile memory pages are mirrored so that certain features of a computer system, such as live migration of applications, fault tolerance, and high availability, will be available even when nonvolatile memory is local to the computer system. Mirroring may be carried out when a cache flush instruction is executed to flush contents of the cache into nonvolatile memory. In addition, mirroring may be carried out asynchronously with respect to execution of the cache flush instruction by retrieving content that is to be mirrored from the nonvolatile memory using memory addresses of the nonvolatile memory corresponding to target memory addresses of the cache flush instruction. | 04-02-2015 |
20150161055 | TRACKING GUEST MEMORY CHARACTERISTICS FOR MEMORY SCHEDULING - A system and method are disclosed for improving operation of a memory scheduler operating on a host machine supporting virtual machines (VMs) in which guest operating systems and guest applications run. For each virtual machine, the host machine hypervisor categorizes memory pages into memory usage classes and estimates the total number of pages for each memory usage class. The memory scheduler uses this information to perform memory reclamation and allocation operations for each virtual machine. The memory scheduler further selects between ballooning reclamation and swapping reclamation operations based in part on the numbers of pages in each memory usage class for the virtual machine. Calls to the guest operating system provide the memory usage class information. Memory reclamation not only can improve the performance of existing VMs, but can also permit the addition of a VM on the host machine without substantially impacting the performance of the existing and new VMs. | 06-11-2015 |
20150161056 | TRACKING GUEST MEMORY CHARACTERISTICS FOR MEMORY SCHEDULING - A system and method are disclosed for improving operation of a memory scheduler operating on a host machine supporting virtual machines (VMs) in which guest operating systems and guest applications run. For each virtual machine, the host machine hypervisor categorizes memory pages into memory usage classes and estimates the total number of pages for each memory usage class. The memory scheduler uses this information to perform memory reclamation and allocation operations for each virtual machine. The memory scheduler further selects between ballooning reclamation and swapping reclamation operations based in part on the numbers of pages in each memory usage class for the virtual machine. Calls to the guest operating system provide the memory usage class information. Memory reclamation not only can improve the performance of existing VMs, but can also permit the addition of a VM on the host machine without substantially impacting the performance of the existing and new VMs. | 06-11-2015 |
20160085571 | Adaptive CPU NUMA Scheduling - Examples perform selection of non-uniform memory access (NUMA) nodes for mapping of virtual central processing unit (vCPU) operations to physical processors. A CPU scheduler evaluates the latency between various candidate processors and the memory associated with the vCPU, and the size of the working set of the associated memory, and the vCPU scheduler selects an optimal processor for execution of a vCPU based on the expected memory access latency and the characteristics of the vCPU and the processors. Some examples contemplate monitoring system characteristics and rescheduling the vCPUs when other placements may provide improved performance and/or efficiency. | 03-24-2016 |
Patent application number | Description | Published |
20090282852 | Thin Film Thermoelectric Devices for Hot-Spot Thermal Management in Microprocessors and Other Electronics - A structure, system and method for controlling a temperature of a heat generating device in a solid medium, wherein heat is extracted from the medium into at least one heat extraction device, the heat extraction device dissipates heat into an environment apart from the medium by a heat sink thermally coupled to the heat extraction device; and heat from the medium is dissipated into the heat sink by a first thermal interface material thermally coupling the heat sink to the medium. | 11-19-2009 |
20100257871 | Thin film thermoelectric devices for power conversion and cooling - A thermoelectric device having at least one thermoelectric unit including at least one thermoelectric pair of n-type and p-type thermoelements, a first header coupled to one side of the thermoelectric pair, and a second header coupled to a second side of the thermoelectric pair. The thermoelectric pair has a thermal conduction channel area smaller than an area of the first header or the second header such that the thermal conduction area is a fraction of the area of the first header or the second header. | 10-14-2010 |
20110198570 | SELF ASSEMBLED NANO DOTS (SAND) AND NON-SELF ASSEMBLED NANO-DOTS (NSAND) DEVICE STRUCTURES AND FABRICATION METHODS THEREOF TO CREATE SPACERS FOR ENERGY TRANSFER - A structure and method for transferring electronic charge or heat or light between substrates. The structure includes first and second substrates separated from one another and a plurality of localized spacers connecting the first and second substrates together. At least one of the localized spacers having a lateral dimension less than 350 nm. A sub-micron separation distance between the first and second substrates is configured to provide carrier tunneling or to provide heat transfer or light transfer between the first and second substrates. The method provides charge carriers or heat or light to a first substrate. The first substrate is separated from a second substrate by at least one localized spacer having a lateral dimension less than 350 nm and tunnels the charge carriers or couples the heat or couples light from the first substrate to the second substrate across a sub-micron gap between the first and second substrates formed by the at least one localized spacer. | 08-18-2011 |
20130180560 | NANOSCALE, ULTRA-THIN FILMS FOR EXCELLENT THERMOELECTRIC FIGURE OF MERIT - A thermoelectric structure including a thermoelectric material having a thickness less than 50 nm and a semi-insulating material in electrical contact with the thermoelectric material. The thermoelectric material and the semi-insulating materials have an equilibrium Fermi level, across a junction between the thermoelectric material and the semi-insulating material, which exists in a conduction band or a valence band of the thermoelectric material. The thermoelectric structure is for thermoelectric cooling and thermoelectric power generation. | 07-18-2013 |
20130186449 | RARE EARTH-DOPED MATERIALS WITH ENHANCED THERMOELECTRIC FIGURE OF MERIT - A thermoelectric material and a thermoelectric converter using this material. The thermoelectric material has a first component including a semiconductor material and a second component including a rare earth material included in the first component to thereby increase a figure of merit of a composite of the semiconductor material and the rare earth material relative to a figure of merit of the semiconductor material. The thermoelectric converter has a p-type thermoelectric material and a n-type thermoelectric material. At least one of the p-type thermoelectric material and the n-type thermoelectric material includes a rare earth material in at least one of the p-type thermoelectric material or the n-type thermoelectric material. | 07-25-2013 |
20140318593 | NANOPARTICLE COMPACT MATERIALS FOR THERMOELECTRIC APPLICATION - A thermoelectric composite and a thermoelectric device and a method of making the thermoelectric composite. The thermoelectric composite is a semiconductor material formed from mechanically-alloyed powders of elemental constituents of the semiconductor material to produce nano-particles of the semiconductor material, and compacted to have at least a bifurcated grain structure. The bifurcated grain structure has at least two different grain sizes including small size grains in a range of 2-200 nm and large size grains in a range of 0.5 to 5 microns. The semiconductor material has a figure of merit ZT, defined as a ratio of the product of square of Seebeck coefficient, S | 10-30-2014 |
20150048028 | Water Purifier with Integrated Power Generator - A water filtration system with power generating capability includes a membrane that receives relatively hot water on a dirty side, purifies the hot water, and transmits it to a clean side having relatively cold purified water. The system further includes at least one thermoelectric element coupled to the membrane that absorbs thermal energy from the dirty side and emits thermal energy into the clean side to generate electrical power. The system further includes at least one conductor electrically coupled to the at least one thermoelectric element that channels generated electrical power away from the at least one thermoelectric element. | 02-19-2015 |
Patent application number | Description | Published |
20100155911 | ESD Protection Diode in RF pads - A diode is provided. The diode includes first and second diffusion layers formed in a substrate, a first metal coupled to the first diffusion layer, and a second metal coupled to the second diffusion layer that has width that is smaller than a width of the second diffusion layer. | 06-24-2010 |
20100246074 | ESD Protection scheme for designs with positive, negative, and ground rails - Apparatuses and systems for dissipating ESD events are provided. In an embodiment, an integrated circuit (IC) device, includes a ground rail, a positive supply rail, a negative supply rail, a circuit block, a plurality of contact pads, and a coupling system. Each of the ground rail, positive supply rail, negative supply rail, and the circuit block are coupled to a respective contact pad of the plurality of contact pads. The contact pad coupled to the circuit block is configured to swing from a voltage of the negative rail to a voltage of the positive rail. The coupling system couples each contact pad of the plurality of contact pads to all other contact pads of the plurality of contact pads, whereby an electrostatic discharge (ESD) event between two contacts pads of the plurality of contact pads can be dissipated. | 09-30-2010 |
20140126095 | ESD PROTECTION SCHEME FOR DESIGNS WITH POSITIVE, NEGATIVE, AND GROUND RAILS - Apparatuses and systems for dissipating ESD events are provided. In an embodiment, an integrated circuit (IC) device, includes a ground rail, a positive supply rail, a negative supply rail, a circuit block, a plurality of contact pads, the circuit block being configured to output an output voltage via a first contact pad of the plurality of contact pads and a range of the output voltage being is between a voltage of the positive supply rail and a voltage of the negative supply rail, and a coupling system that couples the first contact pad to a second contact pad of the plurality of contact pads so as to dissipate an electrostatic discharge (ESD) event between the first and second contact pads. | 05-08-2014 |
Patent application number | Description | Published |
20120079102 | Requester Based Transaction Status Reporting in a System with Multi-Level Memory - A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed. | 03-29-2012 |
20120191915 | EFFICIENT LEVEL TWO MEMORY BANKING TO IMPROVE PERFORMANCE FOR MULTIPLE SOURCE TRAFFIC AND ENABLE DEEPER PIPELINING OF ACCESSES BY REDUCING BANK STALLS - The level two memory of this invention supports coherency data transfers with level one cache and DMA data transfers. The width of DMA transfers is 16 bytes. The width of level one instruction cache transfers is 32 bytes. The width of level one data transfers is 64 bytes. The width of level two allocates is 128 bytes. DMA transfers are interspersed with CPU traffic and have similar requirements of efficient throughput and reduced latency. An additional challenge is that these two data streams (CPU and DMA) require access to the level two memory at the same time. This invention is a banking technique for the level two memory to facilitate efficient data transfers. | 07-26-2012 |
20120290755 | Lookahead Priority Collection to Support Priority Elevation - A queuing requester for access to a memory system. Transaction requests received from two or more requestors access to the memory system. Each transaction request includes an associated priority value. A request queue is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system uses the selected priority value. | 11-15-2012 |
20120297225 | Reducing Current Leakage in L1 Program Memory - An embodiment of the invention provides a method for decreasing power in an L1 program memory of a multi-level memory system. The power is decreased by enabling a sleep mode in the L1 program memory. The sleep mode determines when the L1 program memory will not be accessed for a period of time. When it is determined that the L1 program memory will not be accessed for a period of time, the voltage applied to the memory array is reduced. When it is determined that the L1 program memory will be accessed, the voltage applied to the memory array is increased. | 11-22-2012 |
20120314833 | Integer and Half Clock Step Division Digital Variable Clock Divider - A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio. | 12-13-2012 |
20120324175 | Multi-Port Register File with an Input Pipelined Architecture with Asynchronous Reads and Localized Feedback - In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored. | 12-20-2012 |
20130021858 | Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System - In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency. | 01-24-2013 |
20130036337 | Clock Control of Pipelined Memory for Improved Delay Fault Testing - In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank. | 02-07-2013 |
20130176060 | Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing - This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence. | 07-11-2013 |
20130243148 | Integer and Half Clock Step Division Digital Variable Clock Divider - A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer. | 09-19-2013 |
20130283002 | Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System - In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency. | 10-24-2013 |
Patent application number | Description | Published |
20140243964 | SUTURELESS PROSTHETIC DEVICE - A prosthetic device for use in an anatomical orifice or lumen of a patient includes an expandable first stent structure coupled to a valve support structure having at least one leaflet. The stent structure includes a collar provided with at least one groove or opening adapted to engage a tab extending from the valve support structure. Rotation of the stent structure and valve support structure relative to one another assembles the prosthetic valve device. The prosthetic valve device may be used for sutureless treatment of various valvular conditions such as aorta stenosis and mitral valve replacement. | 08-28-2014 |
20140243969 | PROSTHETIC HEART VALVE WITH EXPANDABLE MICROSPHERES - A prosthetic heart valve includes a valve assembly mounted to an expandable stent. The prosthetic heart valve includes a cuff coupled to the stent. The cuff includes a pocket formed between an outer side and an inner side of the cuff. The pocket includes a plurality of biocompatible and irreversibly expandable microspheres. After implantation of the prosthetic heart valve into a patient, any gaps existing between the cuff and the native heart valve are exposed to bodily fluid, such as blood. The blood enters the pocket of the cuff through pores in the outer side of the cuff. The blood interacts with the microspheres, causing irreversible expansion of the microspheres. The microspheres expand to fill any gaps between the prosthetic heart valve and the native heart tissue, sealing the gaps and preventing leakage through the gaps. | 08-28-2014 |
20150223729 | SYSTEM AND METHOD FOR ASSESSING DIMENSIONS AND ECCENTRICITY OF VALVE ANNULUS FOR TRANS-CATHETER VALVE IMPLANTATION - A system for detecting the dimensions and geometry of a native valve annulus for trans-catheter valve implantation includes a compliant balloon and a shaft within the balloon. One or more drive electrodes may be affixed to a surface of the balloon, and one or more sense electrodes may be affixed to the shaft. After insertion of the balloon into the native valve annulus, the drive electrodes may be energized with a predetermined voltage. Using a trained statistical model and the voltages measured at the sense electrodes, initial estimates of the cross-section of the valve annulus may be obtained. The initial estimates may then be provided to an optimization model of the valve annulus to obtain a highly accurate prediction of the cross-section of the valve annulus. | 08-13-2015 |
20150282932 | CUFF CONFIGURATIONS FOR PROSTHETIC HEART VALVE - A prosthetic heart valve includes a collapsible and expandable stent having a proximal end, a distal end, an annulus section adjacent the proximal end and an aortic section adjacent the distal end. The stent is formed of a plurality of struts. A cuff is coupled to the stent. The cuff has one or more features configured to reduce abrasion and/or perivalvular leakage. | 10-08-2015 |
20150359629 | TWO STAGE ANCHOR AND MITRAL VALVE ASSEMBLY - Systems and methods for medical interventional procedures, including approaches to valve implantation. In one aspect, the methods and systems involve a modular approach to mitral valve therapy. | 12-17-2015 |
20160113768 | SYSTEMS AND METHODS FOR HEART VALVE THERAPY - Prosthetic mitral valves described herein can be deployed using a transcatheter mitral valve delivery system and technique to interface and anchor in cooperation with the anatomical structures of a native mitral valve. This document describes prosthetic heart valve designs that interface with native mitral valve structures to create a fluid seal, thereby minimizing mitral regurgitation and paravalvular leaks. This document also describes prosthetic heart valve designs and techniques to manage blood flow through the left ventricular outflow tract. In addition, this document describes prosthetic heart valve designs and techniques that reduce the risk of interference between the prosthetic valves and chordae tendineae. | 04-28-2016 |
Patent application number | Description | Published |
20140012367 | BALLOON SIZING DEVICE AND METHOD OF POSITIONING A PROSTHETIC HEART VALVE - A sizing device for a collapsible prosthetic heart valve, the sizing device includes a collapsible and expandable balloon having a proximal end, a distal end. At least one microelectromechanical sensor is coupled to the balloon, the at least one sensor being capable of measuring information related to size and stiffness of tissue. | 01-09-2014 |
20140107768 | SIZING DEVICE AND METHOD OF POSITIONING A PROSTHETIC HEART VALVE - A sizing device for a collapsible prosthetic heart valve includes a collapsible and expandable stent. A microelectromechanical sensor is coupled to the stent, the sensor being capable of collecting information related to the size and stiffness of tissue. | 04-17-2014 |
20140213918 | TISSUE SENSING DEVICE FOR SUTURELESS VALVE SELECTION - A sensing device for a collapsible prosthetic heart valve, the sensing device including an elongated shaft having a proximal end and a distal end, a sensing body coupled to the distal end of the shaft, the sensing body being adapted to fit within a native valve annulus and at least one microelectromechanical sensor attached to the sensing body, the at least one sensing body being capable of measuring a property of tissue. | 07-31-2014 |
20140277417 | CUFF CONFIGURATIONS FOR PROSTHETIC HEART VALVE - A prosthetic heart valve includes a collapsible and expandable stent having a proximal end, a distal end, an annulus section adjacent the proximal end and an aortic section adjacent the distal end. The stent is formed of a plurality of struts. A cuff is coupled to the stent. The cuff has one or more features configured to reduce abrasion and/or perivalvular leakage. | 09-18-2014 |
Patent application number | Description | Published |
20080243980 | Coupling Simulations With Filtering - Systems, techniques, and machine-readable instructions for coupling simulations with filtering. In one aspect, a method is for coupling simulations with filtering of data. The method includes generating a first visual rendition of a first collection of display data and a second visual rendition of a second collection of display data, receiving user input changing a variable rendered in the second visual rendition, and representing an impact of the change to the variable on the first visual rendition of the first collection of display data. The second collection of display data is a product of filtering the first collection of display data. | 10-02-2008 |
20080244379 | DISPLAYING DETAILED INFORMATION IN THE CONTEXT OF A CONDENSED ENUMERATION OF INFORMATION - Systems and techniques for displaying detailed information in the context of a condensed enumeration of information. For example, in one aspect, in one aspect, a display includes a visual rendition of a table that systematically arranges condensed information in a collection of rows and columns for reference by a human user. The table includes information characterizing a collection of items. The visual rendition of the table comprises a region that renders additional detail regarding a first item in the collection. The region is disposed in the midst of the visual rendition of the table. | 10-02-2008 |
20140067633 | System and Method for Management and Verification of Invoices - Embodiments of the present invention include architectures and methods for automated management of invoices. Embodiments of the present invention may include techniques for receiving and unifying invoice data, retrieving information about each invoice, verifying each invoice and resolving invoice exceptions. The present invention includes software components for efficiently processing invoices. In other embodiments, the present invention includes methods of processing an invoice. | 03-06-2014 |