Patent application number | Description | Published |
20100332887 | STORAGE CONTROL DEVICE HAVING CONTROLLER OPERATED ACCORDING TO DETECTION SIGNAL DERIVED FROM MONITORING POWER SIGNAL AND RELATED METHOD THEREOF - One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range. | 12-30-2010 |
20120112794 | DIFFERENTIAL DRIVER WITH CALIBRATION CIRCUIT AND RELATED CALIBRATION METHOD - A calibration circuit for calibrating a differential driver with a differential output port including a first output node and a second output node includes: a comparing circuit arranged to receive a first output voltage corresponding to the first output node and a second output voltage corresponding to the second output node, and generate a comparison result according to the first output voltage, the second output voltage, and a predetermined voltage; and a controlling circuit coupled to the comparing circuit, a first resistive element and a second resistive element. The controlling circuit is arranged to adjust the first resistive element and the second resistive element according to the comparison result, wherein the first resistive element is coupled between the first output node and a reference voltage, and the second resistive element is coupled between the second output node and the reference voltage. | 05-10-2012 |
20120177146 | DETECTING CIRCUIT AND RELATED DETECTING METHOD - A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair. | 07-12-2012 |
20120300831 | METHODS FOR PERFORMING ADAPTIVE EQUALIZATION AND ASSOCIATED APPARATUS - A method for performing adaptive equalization includes: dynamically detecting current levels of a plurality of sets of pattern levels respectively corresponding to a plurality of data patterns, wherein each set of the sets of pattern levels includes a previous level, a current level, and a next level respectively corresponding to one of the plurality of data patterns; and dynamically calculating a plurality of data decision levels according to the current levels of the sets of pattern levels, for use of data decision, wherein each data decision level of at least one portion of the plurality of data decision levels is not equal to zero, and the data decision levels are dynamically adjusted in accordance with the current levels of the sets of pattern levels, in order to enhance a signal-to-noise ratio (SNR). An associated method for performing adaptive equalization is also provided. Associated apparatus are also provided. | 11-29-2012 |
20130322577 | DETECTING CIRCUIT AND RELATED DETECTING METHOD - A detecting circuit includes: a first offset generating circuit, arranged to apply a first offset to an input signal pair and accordingly generate a first output signal pair; and a first sampling circuit, coupled to the first offset generating circuit, the first sampling circuit arranged to sample the first output signal pair to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair, and the first sampling circuit is controlled by a first signal that is irrelevant to the input signal pair. | 12-05-2013 |
20140145708 | DETECTING CIRCUIT AND RELATED CIRCUIT DETECTING METHOD - A detecting circuit includes: a testing signal generator, arranged to selectively generate a testing signal having a first signal edge or a second signal edge to a connecting port; and a detector, arranged to detect a first detect signal on the connecting port after the testing signal having the first signal edge is coupled to the connecting port, and to detect a second detect signal on the connecting port after the testing signal having the second signal edge is coupled to the connecting port; wherein the detector is further arranged to determine if an external circuit element is coupled between the connecting port and a reference voltage according to the first detect signal and the second detect signal. | 05-29-2014 |
20140203858 | INTERPOLATOR AND INTERPOLATION CELLS WITH NON-UNIFORM DRIVING CAPABILITIES THEREIN - An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal. | 07-24-2014 |
Patent application number | Description | Published |
20090168943 | CLOCK GENERATION DEVICES AND METHODS - A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal. | 07-02-2009 |
20090184732 | DIFFERENTIAL DRIVING CIRCUIT CAPABLE OF OPERATING AT LOW SUPPLY VOLTAGE WITHOUT REQUIRING COMMON MODE REFERENCE VOLTAGE - A driving circuit includes a pair of input ports, a pair of differential output ports, a first differential pair, a second differential pair, a load unit, and a current source. The first differential pair is directly connected to a first voltage level, and is coupled to the pair of input ports and the pair of differential output ports. The second differential pair is coupled to the pair of input ports and the pair of differential output ports. The load unit is coupled to the pair of differential output ports. The current source is coupled between the second differential pair and a second voltage level. | 07-23-2009 |
20090195288 | SERIAL LINK TRANSMITTER - The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver. | 08-06-2009 |
20090278574 | Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider - A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal. | 11-12-2009 |
20090296869 | COMMUNICATION SYSTEMS, CLOCK GENERATION CIRCUITS THEREOF, AND METHOD FOR GENERATING CLOCK SIGNAL - A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration. | 12-03-2009 |
20090296870 | COMMUNICATION SYSTEMS AND CLOCK GENERATION CIRCUITS THEREOF WITH REFERENCE SOURCE SWITCHING - A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL switches to generate the output clock signal according to a second clock signal. | 12-03-2009 |