Patent application number | Description | Published |
20090109762 | METHOD FOR PROGRAMMING NON-VOLATILE MEMORY - A method for programming non-volatile memory utilizes substrate hot carrier effect to conduct programming operations. A forward bias voltage is applied between an N-type well region and a P-type well region so as to inject electrons in the N-type well region into the P-type well region. After that, the electrons are accelerated by a depletion region established by a voltage applied to a source region and a drain region, and a vertical electrical field established between a control gate and the P-type well region further forces the electrons to be injected into a charge storage layer. Since the present invention adopts the substrate hot carrier effect to inject carriers into the charge storage layer, the required program operation voltage is low, which benefits to save power consumption and enhance the reliability of the device. | 04-30-2009 |
20140091273 | RESISTIVE RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line. | 04-03-2014 |
20150072500 | METHOD FOR FABRICATING RESISTIVE RANDOM ACCESS MEMORY - A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes. | 03-12-2015 |
20150303199 | MEMORY STRUCTRUE AND OPERATION METHOD THEREOF - This invention provides a memory structure and an operation method thereof. The memory structure includes a triode for alternating current (TRIAC) and a memory cell. The memory cell is electrically connected to the TRIAC. | 10-22-2015 |
Patent application number | Description | Published |
20080237854 | METHOD FOR FORMING CONTACT PADS - First, a substrate having a conductor therein is provided. Next, a first dielectric layer is disposed on the conductor and the substrate and a first opening is formed in the first dielectric layer for exposing the conductor. A first metal layer is deposited over the surface of the first dielectric layer and into the first opening. Next, an etching stop layer and a second metal layer are deposited over the surface of the first metal layer, and a pattern transfer process is performed by using a second dielectric layer as a mask to remove a portion of the first metal layer, the etching stop layer, and the second metal layer for exposing the first dielectric layer. A passivation layer is disposed on the second metal layer and the first dielectric layer and a second opening is formed in the passivation layer to expose a portion of the second metal layer. | 10-02-2008 |
20080246144 | METHOD FOR FABRICATING CONTACT PADS - A method for fabricating a contact pad is disclosed. A first metal layer is disposed on a substrate for serving as a probing region. A second metal layer is disposed on the substrate thereafter to serve as an electrical connection region. Preferably, the first metal layer and the second metal layer are composed of different material and are electrically connected. The present invention uses two different metals to form a probing region and an electrical connection region of a contact pad. The probing region is used for providing a contacting surface for a test probe, whereas the electrical connection region is used for establishing an electrical connection in the later bumping or wire bonding process. By providing a contact pad having two different regions, the present invention is able to achieve probing process while prevent the surface of the contact pad from being damaged by the contact of test probes. | 10-09-2008 |
20080303177 | BONDING PAD STRUCTURE - A bonding pad structure including a bonding pad and a passivation layer is described. The bonding pad is disposed on a chip. The passivation layer covers the bonding pad. In addition, the passivation layer has a first opening exposing a bonding region of the bonding pad and a second opening exposing a probing region of the bonding pad, respectively. | 12-11-2008 |
20090033346 | GROUP PROBING OVER ACTIVE AREA PADS ARRANGEMENT - A group probing over active area (POAA) pads arrangement includes a chip having a set of bonding pads, at least a first set of probing pads and a second set of probing pads. Each of the first set of probing pads and the second set of probing pads are electrically connected to one of the corresponding bonding pads, respectively. And each of the first set of probing pads and the second set of probing pads are interlaced in a diagonal line pattern. According to a concept of grouping and interlacing the probing pads, each bonding pad obtains at least two probing pads. Therefore times of test probing performed on each probing pad are reduced and repeated probe's pressures toward inter metal dielectric (IMD) layers underneath the probing pads are consequently reduced. | 02-05-2009 |
Patent application number | Description | Published |
20120063019 | CONTROL METHOD FOR A VOICE COIL MOTOR AND LENS FOCUSING SYSTEM USING THE SAME - A control method is provided to reduce the spring resonance of a voice coil motor when the coil current of the voice coil motor is changed. Each time a total variation for the coil current to be changed is identified and divided into a plurality of step variations applied one by one with a time step equal to one half of the spring resonant period of the voice coil motor. Due to reduction of the spring resonance, the control method speed up the voice coil motor to a steady state. With this control method, a lens focusing system has a shorter focusing time. | 03-15-2012 |
20120098584 | CIRCUIT AND METHOD FOR IMPROVEMENT OF A LEVEL SHIFTER - A current limiter is connected between a voltage source and the level shifting latch of a level shifter for limiting the driving current for the level shifting latch under a threshold, to thereby reduce the current consumption of the level shifter during logic transition, by which the level shifting latch can be implemented by transistors with shorter channels, thereby downsizing the circuit area of the level shifter. Preferably, the threshold is adjustable for adjusting the output driving capability of the level shifter and speeding up logic transition of the level shifter. | 04-26-2012 |
20120249511 | SOURCE DRIVER FOR AN LCD PANEL - A source driver for an LCD panel includes two gm stages and two output buffers. In a normal operation mode, the first gm stage and the first output buffer establish a unity gain buffer to amplify a positive polarity analog voltage to be a positive polarity output voltage, and the second gm stage and the second output buffer establish a unity gain buffer to amplify a negative polarity analog voltage to be a negative polarity output voltage. In a polarity inversion mode, the second gm stage and the first output buffer establish a unity gain buffer to amplify a positive polarity analog voltage to be a positive polarity output voltage, and the first gm stage and the second output buffer establish a unity gain buffer to amplify a negative polarity analog voltage to be a negative polarity output voltage. | 10-04-2012 |
Patent application number | Description | Published |
20090153532 | PIXEL-DRIVING METHOD AND CIRCUIT THEREOF - A method for driving pixel, being compatible between dot-inversion driving mechanism and dual-gate driving mechanism, includes setting four continuous pixels as a driving sub-unit, having a first pixel transistor, a second pixel transistor, a third pixel transistor, and a fourth pixel transistor. The first gate line commonly controls two gates of the first and fourth pixel transistors. The second gate line commonly controls two gates of the second and third pixel transistors. The first source line commonly controls two sources of the first and second pixel transistors. The second source line commonly controls two sources of the third and fourth pixel transistors. A positive voltage and a negative voltage are alternatively in time sequence applied to the first and second source lines, respectively. An activate voltage is alternatively in time sequence applied to the first and second source lines, respectively. | 06-18-2009 |
20130321036 | GATE DRIVING APPARATUS - A gate driving apparatus is disclosed. The gate driving apparatus includes a first gate driving chip and N second gate driving chips, wherein N is positive integer. The first gate driving chip has a first input pin and a first current output pin. The first gate driving chip receives a reference electrical signal by the first input pin, and generates a reference current according to the reference electrical signal. The first current output pin is used for outputting the reference current. Each of the second gate driving chips has a current input pin for receiving the reference current and a second current output pin for outputting the reference current. The first gate driving chip and the second gate driving chips generate at least a first output signal and at least N second output signals according to the reference current. | 12-05-2013 |
20140210521 | GATE OR SOURCE DRIVING APPARATUS - A gate/source driving apparatus includes a first gate/source driving chip and a second gate/source driving chip. The first gate/source driving chip includes a plurality of first charge pump circuits, each of which has a voltage input end, a voltage output end, a first capacitor end, and a second capacitor end. The second gate/source driving chip includes a plurality of second charge pump circuits, each of which also has a voltage input end, a voltage output end, a first capacitor end, and a second capacitor end. The voltage output end of at least one of the first charge pump circuits is coupled to the voltage input end of at least one of the second charge pump circuits. | 07-31-2014 |
20150062190 | LCD DEVICE AND METHOD FOR IMAGE DITHERING COMPENSATION - A liquid crystal display (LCD) device includes: a data source, for generating a N-bit pixel data, N being a positive integer; a digital gamma correction unit, coupled to the data source, for performing digital gamma correction on the pixel data to generate a (N+M)-bit digital gamma correction pixel data, M being a positive integer; an image dithering unit, coupled to the digital gamma correction unit, for performing image dithering on the digital gamma correction pixel data to generate a (N+M−K)-bit dithering compensation pixel data, K being a positive integer; and a converter, coupled to the image dithering unit, for converting the dithering compensation pixel data into an output image. A bit number of the converter is lower than a bit number of the digital gamma correction unit. | 03-05-2015 |
20150102987 | Non-Overlap Data Transmission Method For Liquid Crystal Display And Related Transmission Circuit - The present disclosure provides a non-overlap data transmission method for a liquid crystal display (LCD). The non-overlap data transmission method includes obtaining an entire fame image data; dividing the entire frame image data into a plurality of image data segments and individually sending the image data segments to a plurality of display processing units at the same time, wherein each of the image data segments is sent to one of the display processing units and image data of each image data segment does not overlap with image data of the other image data segments; and mutually sending image data of the image data segments through the display processing units. | 04-16-2015 |
20150214942 | GATE DRIVING APPARATUS - A gate driving apparatus is disclosed. The gate driving apparatus includes a first gate driving chip and N second gate driving chips, wherein N is positive integer. The first gate driving chip has a first input pin and a first current output pin. The first gate driving chip receives a reference electrical signal by the first input pin, and generates a reference current according to the reference electrical signal. The first current output pin is used for outputting the reference current. Each of the second gate driving chips has a current input pin for receiving the reference current and a second current output pin for outputting the reference current. The first gate driving chip and the second gate driving chips generate at least a first output signal and at least N second output signals according to the reference current. | 07-30-2015 |
Patent application number | Description | Published |
20120220070 | METHOD OF MANUFACTURING SOLAR CELL - A method of manufacturing a solar cell includes the following steps. An ion implantation process is performed to a first surface of a substrate to form a first doping layer. Then, the ion implantation process is performed to a second surface of the substrate to form a second doping layer. After that, an annealing process is performed to the structure formed by the substrate, the first doping layer and the second doping layer, and forming a first passivation layer on the first doping layer and a second passivation layer on the second doping layer by the annealing process. A third passivation layer is formed on the first passivation layer formed after the annealing process and a fourth passivation layer is formed on the second passivation layer formed after the annealing process. Afterward, conductive electrodes are formed on the third passivation layer and the fourth passivation layer, respectively. | 08-30-2012 |
20120255592 | PHOTOVOLTAIC PANEL AND MANUFACTURING METHOD THEREOF - A photovoltaic panel includes a photovoltaic array, an electrically conductive busbar, a plurality of electrically conductive fingers and an electrically conductive ribbon. The electrically conductive busbar is disposed on the photovoltaic array and having a plurality of connection ribs. The electrically conductive fingers are disposed on the photovoltaic array and connected with the connection ribs respectively. The electrically conductive ribbon is soldered on the electrically conductive busbar, wherein a gap is formed between each electrically conductive finger and the electrically conductive ribbon. | 10-11-2012 |
20160118510 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell includes a semiconductor substrate, a boron back surface field (BSF) layer, a passivation layer, a back electrode layer and an aluminum local BSF layer. The semiconductor substrate has a front surface and a back surface opposite to each other. The boron BSF layer is disposed in the semiconductor substrate beneath the back surface. The passivation layer is disposed over the boron BSF layer and has an opening through the passivation layer. The back electrode layer is disposed in the opening. The aluminum local BSF layer is disposed in the semiconductor substrate beneath the opening and in contact with the boron BSF layer and the back electrode layer. | 04-28-2016 |
Patent application number | Description | Published |
20100285626 | FABRICATION METHOD OF LIGHT EMITTING DIODE - A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers and a plurality of quantum well layers on the first type doped semiconductor layer. The quantum well layers are formed at a growth temperature T | 11-11-2010 |
20120153339 | LIGHT-EMITTING DIODE CHIP STRUCTURE AND FABRICATION METHOD THEREOF - A light-emitting diode chip structure including a conductive substrate, a semiconductor stacking layer and a patterned seed crystal layer is provided. The conductive substrate has a surface. The surface has a first region and a second region alternately distributed over the surface. The semiconductor stacking layer is disposed on the conductive substrate, and the surface of the conductive substrate faces the semiconductor stacking layer. The patterned seed crystal layer is disposed on the first region of the surface of the conductive substrate and between the conductive substrate and the semiconductor stacking layer. The patterned seed crystal layer separates the semiconductor stacking layer from the first region. The semiconductor stacking layer covers the patterned seed crystal layer and the second region, and is electrically connected to the conductive substrate through the second region. A fabrication method of the light-emitting diode chip structure is also provided. | 06-21-2012 |
20130320372 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode, comprising a light emitting diode (LED) cell, a dielectric layer and a metal layer is provided. The LED cell has a top surface, a bottom surface, a first lateral surface and a second lateral surface. The bottom surface is opposite to the top surface. The second lateral surface is opposite to the first lateral surface. An electrode layer is disposed on the top surface. The dielectric layer is disposed on the bottom surface, the first lateral surface and the second lateral surface. The metal layer is disposed on the dielectric layer and electrically insulated from the electrode layer. | 12-05-2013 |
Patent application number | Description | Published |
20100288345 | QUANTUM DOT THIN FILM SOLAR CELL - A quantum dot thin film solar cell is provided, which at least includes a first electrode layer, an optical active layer, and a second electrode layer sequentially deposited on a substrate. A plurality of quantum dots is formed in the optical active layer. Since the plurality of quantum dots and the optical active layer are formed through co-sputtering, an interface adhesion between the plurality of quantum dots and the optical active layer is good in this quantum dot thin film solar cell. | 11-18-2010 |
20110120540 | QUANTUM DOT DYE-SENSITIZED SOLAR CELL - A quantum dot dye-sensitized solar cell (QDDSSC) including an anode, a cathode, and an electrolyte between the anode and the cathode is provided. The anode includes a semiconductor electrode layer adsorbed with a dye, a plurality of quantum dots distributed within the semiconductor electrode layer, and a plurality of metal nanoparticles distributed within the semiconductor electrode layer. Because the absorption spectra of the quantum dots, the dye, and the semiconductor electrode layer cover the infrared (IR), visible, and ultraviolet (UV) regions of the solar spectrum, IR to UV light in the solar spectrum can be effectively absorbed, and accordingly the conversion efficiency of the solar cell can be improved. Moreover, the metal nanoparticles can increase the light utilization efficiency. | 05-26-2011 |
20110303528 | METHOD AND APPARATUS FOR SPUTTERING FILM CONTAINING HIGH VAPOR PRESSURE MATERIAL - A method and an apparatus for sputtering a film containing high vapor pressure material are provided. The apparatus includes a chamber, a sputtering gun installed in the chamber, a complex target disposed on the sputtering gun, and a substrate holder. The complex target includes a main target and a plurality of pellets, and a material of the pellets is at least one high vapor pressure material that is a material with a vapor pressure greater than 1×10 | 12-15-2011 |
20120001550 | MAGNETIC MODUE OF ELECTRON CYCLOTRON RESONANCE AND ELECTRON CYCLOTRON RESONANCE APPARATUS USING THE SAME - The present invention provides a magnetic module for electron cyclotron resonance (ECR) and ECR apparatus using the magnetic module, wherein the magnetic module comprises a plurality of layers of supporting ring and a plurality of magnetic pillars. Each of the supporting rings has an outer surface and an inner surface and has a plurality of through holes radially disposed inside the supporting ring. The plurality of pillars are respectively embedded into the plurality of through holes of each supporting ring and magnetic fields of the magnetic pillars in each two adjacent supporting ring are respectively opposite to each other. The ECR apparatus of the present invention is capable of being operated under lower pressure environment for forming a single atom layer on a substrate. | 01-05-2012 |
20120177542 | MICROWAVE-EXCITED PLASMA DEVICE - A microwave-excited plasma device is proposed. The device comprises of a plurality of microwave plasma reaction units which are capable of generating plasma independently such that a large-area plasma is able to be generated by all of the units. Besides, the high cost of the large-area microwave coupling window and its deformation together with possible breakage caused by atmospheric pressure can be prevented. Moreover, when a plurality of permanent magnets is assembled upon each of the plasma reaction units, the microwave-excited plasma device is improved to be a large-area electron cyclotron resonance (ECR) plasma device. | 07-12-2012 |
20130129974 | ZINC OXIDE ANTI-REFLECTION LAYER HAVING A SYRINGE-LIKE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The disclosure provides a zinc oxide anti-reflection layer having a syringe-like structure and method for fabricating the same. The zinc oxide anti-reflection layer includes: a zinc oxide lower portion, wherein the zinc oxide lower portion has a nanorod array structure; and a zinc oxide upper portion connected to the zinc oxide lower portion, wherein the zinc oxide anti-reflection layer has a syringe-like structure. | 05-23-2013 |
20130157868 | METHOD OF JOINING SUPERCONDUCTOR MATERIALS - A method of joining superconductor materials is described. A microwave chamber including a first heat absorption plate and a second heat absorption plate corresponding to the first absorption plate is provided. A first superconductor material and a second superconductor material are disposed between the first heat absorption plate and the second heat absorption plate in the microwave chamber. The first superconductor material and the second superconductor material have an overlapping region therebetween, and a pressure is applied to the first heat absorption plate and the second heat absorption plate. Microwave power is supplied to the microwave chamber. The first heat absorption plate and the second heat absorption plate transform the microwave power into thermal energy so as to join the first superconductor material and the second superconductor material at the overlapping region. | 06-20-2013 |
20130164208 | METHODS OF FORMING GRAPHENE - Disclosed is a method of forming graphene. A graphite positive electrode (or positive electrode together with graphite material) wrapped in a semipermeable membrane and a negative electrode are dipped in an acidic electrolyte to conduct an electrolysis process. As such, a first graphene oxide having a size larger than a pore size of the semipermeable membrane is exfoliated from the graphite positive electrode (or the graphite material). The electrolysis process is continuously conducted until a second graphene oxide is exfoliated from the first graphene oxide, wherein the second graphene oxide has a size which is smaller than the pore size of the semipermeable membrane to penetrate through the semipermeable membrane. The second graphene oxide diffused into the acidic electrolyte outside of the semipermeable membrane is collected. Finally, the collected second graphene oxide is chemically reduced to obtain a graphene. | 06-27-2013 |
20130168229 | METHOD OF PREPARING GRAPHENE LAYER - Disclosed is a method of forming a graphene layer, including: putting a substrate in a chamber of an electron cyclotron resonance device, and then vacuuming the chamber. Conducting a carbon-containing gas into the chamber, wherein the carbon-containing gas has a pressure of 10 | 07-04-2013 |
20140170057 | METHOD AND APPARATUS FOR MANUFACTURING GRAPHENE SHEET - Disclosed is an apparatus for manufacturing graphene sheets. The apparatus includes a gas tube, and a hydrocarbon gas source connected to a front part of the gas tube for providing a hydrocarbon gas through the gas tube. The apparatus also includes a microwave generator to generate a microwave passing a middle part of the gas tube through a waveguide tube to form a microwave plasma torch from the hydrocarbon gas, wherein the hydrocarbon gas is cracked by the microwave plasma torch to form graphene sheets. The apparatus includes a tube collector connected to a back part of the gas tube for collecting the graphene sheets. | 06-19-2014 |
20150024225 | SCREEN PRINTING FILM AND SURFACE MODIFICATION METHOD OF THE SAME - A screen printing film and a surface modification method of the same are provided. The method includes providing a substrate having a PVA film on at least one surface of the substrate. The surface of the substrate is modified by generating a heating source and a plasma source, wherein a heating temperature to the substrate is between 100° C. and 500° C. The step of generating the heating source may be prior to, after, or simultaneous with the step of generating the plasma source. | 01-22-2015 |
20150303368 | METHOD OF REPAIRING DEFECT IN SUPERCONDUCTING FILM, METHOD OF COATING SUPERCONDUCTING FILM, AND SUPERCONDUCTING FILM FORMED BY THE METHOD - A method of repairing defect in a superconducting film, a method of coating a superconducting film, and a superconducting film formed by the method are prepared. The method of repairing defect includes detecting the superconducting film during a manufacturing process thereof. When a defect therein is detected, a repairing structure with superconductivity is formed on a position of the defect. | 10-22-2015 |
Patent application number | Description | Published |
20110057636 | Method for Reducing Energy Loss in DC-DC Converter and Related Control Device and DC-DC Converter - A method for reducing energy loss in a DC-DC converter comprises detecting an output current of the DC-DC converter to generate a sensing signal, adjusting a frequency of an oscillation signal, comparing a reference signal and a feedback signal of the DC-DC converter to generate a comparison result, comparing the comparison result and the oscillation signal to generate a PWM signal, and determining whether an input end of the DC-DC converter is electrically connected to an output end of the DC-DC converter according to the PWM signal. | 03-10-2011 |
20110080755 | Power Supply with Synchronized Clocks and Related DC-DC Converter - A power supply with synchronized clocks includes a transformer for transforming an AC input voltage into a DC input voltage, a delay unit for delaying phase of a standard clock signal to generate a plurality of synchronization clock signals, a major DC-DC converter for adjusting voltage level and phase of the DC input voltage according to one of the plurality of synchronization clock signals to generate a major output voltage, and a plurality of parallel DC-DC converters each for adjusting voltage level and phase of the major output voltage according to one of the plurality of synchronization clock signals to generate a minor output voltage. | 04-07-2011 |
20110095741 | Control Device for DC-DC Converter and Related DC-DC Converter - A control device for a DC-DC converter includes a PWM controller for generating a PWM signal to a switch module of the DC-DC converter according to a feedback signal of the DC-DC converter, a logic circuit for generating a selection signal according to a magnitude of an output current of the DC-DC converter, and a multiplexer coupled to a plurality of voltages for selecting one of the plurality of voltages to be a supply voltage according to the selection signal. | 04-28-2011 |
Patent application number | Description | Published |
20090167285 | RESONANCE CIRCUIT FOR USE IN H-BRIDGE DC-DC CONVERTER - The present invention discloses a resonance circuit for use in an H-bridge DC-DC converter, the resonance circuit comprising: an H-bridge converter, capable of converting unstable DC power into stable DC power; a first resonance circuit, disposed on a buck side of the H-bridge converter for reducing the turn-off loss of a first active switching element; and a second resonance circuit, disposed on a boost side of the H-bridge converter for reducing the turn-on loss of a second active switching element. The H-bridge converter comprises: a first active switching element and a second active switching element; a coupled inductor with dual windings capable of storing energy; and a first passive switching element and a second passive switching element. The first resonance circuit comprises: a first inductor, a second inductor, a first auxiliary inductor, a first passive switching element, a second passive switching element and a first auxiliary capacitor, wherein the second inductor comprises a primary winding and an auxiliary winding. The second resonance circuit comprises: a second auxiliary inductor, a third active switching element, a first auxiliary inductor, a first passive switching element, a fourth passive switching element, a third capacitor, a fourth capacitor and a second auxiliary capacitor. | 07-02-2009 |
20090168460 | APPARATUS FOR CONTROLLING H-BRIDGE DC-AC INVERTER - The present invention discloses an apparatus for controlling an H-bridge DC-AC inverter, comprising an H-bridge DC-DC converting circuit capable of converting unstable DC power into stable DC power and a full-bridge DC-AC inverting circuit capable of inverting DC power output from the H-bridge DC-DC converting circuit into AC power. The H-bridge DC-DC converting circuit comprises: a first active switching element and a second active switching element; an inductor capable of storing energy; a first passive switching element and a second passive switching element; and a first capacitor and a second capacitor. The full-bridge DC-AC inverting circuit comprises: a third active switching element, a fourth active switching element, a fifth active switching element and a sixth active switching element; an output inductor; and an output capacitor. | 07-02-2009 |
20100142233 | POWER CONVERSION DEVICE AND CONTROL METHOD THEREOF - A power conversion device is provided for converting a DC voltage to an alternating current corresponding to an AC voltage according to the AC voltage, which includes a power conversion unit and an output unit. The power conversion unit converts the DC voltage to a high-frequency current having two envelops corresponding to the waveform of the AC voltage. The output unit includes an inductive circuit, a full-wave rectifying circuit, an inverter circuit and a filter circuit. The inductive circuit provides two induced currents according to the high-frequency current, wherein one induced current and the high-frequency current are in phase, and the other induced current and the high-frequency current are in antiphase. The full-wave rectifying circuit full-wave rectifies the two induced currents. The inverter circuit alternatively transfers the two full-wave rectified induced currents, and thus output an output current. The filter circuit filters the output current to provide the alternating current. | 06-10-2010 |
20110103107 | RESONANCE CIRCUIT FOR DC-LINK VOLTAGE CONTROL IN DC-TO-AC INVERTER - The present disclosure relates to a resonance circuit for DC-link voltage control in a DC-to-AC inverter. The resonance circuit comprises two active switches. Before the active switches of the DC-to-AC inverter are turned on, a DC-link voltage is isolated by the active switches and the active switches of the DC-to-AC inverter are discharged by the resonance circuit to zero voltage at both ends. Then, the active switches of the DC-to-AC inverter are turned on again after the DC-link voltage is charged by the resonance circuit until the DC-link voltage restores to a normal voltage value. Hence, the active switches of the DC-to-AC inverter achieve zero-voltage switching. Not only the switching loss can be reduced to enhance the conversion efficiency, but also the electro-magnetic interference as well as the RF interference due to dynamic transient changes of the voltage (dv/dt) and of the current (di/dt) can be lowered. | 05-05-2011 |
20120087157 | DC-TO-AC POWER INVERTING APPARATUS FOR PHOTOVOLTAIC MODULES - The disclosure provides a DC-to-AC power inverting apparatus for photovoltaic modules, which comprises two stages: a first stage including a resonant circuit in series, an isolating transformer with three windings, a full-bridge DC-to-AC converting unit operating in a high-frequency switch mode so as to reduce the transformer volume, and a full-wave rectifier; while a second stage including a half-bridge single-phase inverter unit with two active switches. In the first stage, any high-frequency AC signal produced from the primary winding of the isolating transformer is converter into a DC signal by the full-wave rectifier at the secondary winding of the isolation transformer. Moreover, the switching of the two active switches in the second stage is controlled to operate in a low-frequency mode using a switching frequency synchronized with the frequency of the public electrical supply to control the AC output, and thus to reduce the switching loss of the active switches. | 04-12-2012 |
20130141949 | DC-TO-DC VOLTAGE REGULATOR AND ITS OPERATING METHOD THEREOF - A method for operating the DC-to-DC voltage regulator including plural active switches and plural inductors is disclosed. The method including the steps of: turning on the first active switch, and then turning off the first active switch when the current flowing in the first inductor is equal to zero; turning on the third active switch, and then turning off the third active switch when the current flowing in the second inductor is equal to zero; turning on the second active switch, and then turning off the second active switch when the current flowing in the first inductor is equal to zero; and turning on the fourth active switch, and then turning off the fourth active switch when the current flowing in the second inductor is equal to zero. | 06-06-2013 |