Jung, Icheon-Si
Bo Kyoung Jung, Icheon-Si KR
Patent application number | Description | Published |
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20130037895 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas. | 02-14-2013 |
20130157385 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask. | 06-20-2013 |
Boo Ho Jung, Icheon-Si KR
Patent application number | Description | Published |
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20120061739 | METHOD FOR FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE USING THE SAME - Provided are a method for fabricating a capacitor and a semiconductor device using the same. The semiconductor device includes a MOS transistor capacitor, first and second plate capacitors, and a metal interconnection. The MOS transistor capacitor is arranged between a power supply and a ground. The first and second plate capacitors are arranged between the power supply and the ground. The metal interconnection is configured to connect the first and second plate capacitors. | 03-15-2012 |
20120248586 | SEMICONDUCTOR APPARATUS FOR PREVENTING CROSSTALK BETWEEN SIGNAL LINES - A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of signal lines, and at least one interface member. The signal lines are disposed on the semiconductor substrate. The interface member is disposed in the semiconductor substrate between the adjacent signal lines among the signal lines to pierce the semiconductor substrate. | 10-04-2012 |
20130320504 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING THROUGH SILICON VIAS - A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of through-silicon vias (TSVs) formed in the semiconductor substrate, and an impedance path blocking unit located between the plurality of TSVs. | 12-05-2013 |
20140062557 | METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME - Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result. | 03-06-2014 |
Choong Man Jung, Icheon-Si KR
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20140063993 | REPAIR SYSTEM FOR REPAIRING DEFECT USING E FUSES AND METHOD OF CONTROLLING THE SAME - A system for repairing a plurality of semiconductor chips each comprising a data storage region including electric fuses connected to the data storage regions of the plurality of semiconductor chips, a defect determination unit configured to read the data of a chip that is actually accessed and the data of an idle chip in the data storage regions, compare the actually accessed and read data with the data of the idle chip, and detect a defect based on a result of the comparison, a storage unit configured to store the defective position of the defect according to a result of the defect determination unit, and a repair unit configured to repair the defect through an E fuse connected to the position of the defect using a reset signal. | 03-06-2014 |
Dongjin Jung, Icheon-Si KR
Patent application number | Description | Published |
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20090166835 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER - An integrated circuit package system including: providing a base substrate; coupling a base integrated circuit on the base substrate; forming a double side molded interposer unit over the base integrated circuit including: providing an interposer substrate having an interposer top and an interposer bottom, mounting a first integrated circuit to the interposer bottom and electrically connected thereto, mounting a second integrated circuit to the interposer top and electrically connected thereto, and molding a first chip cover on the first integrated circuit and a second chip cover on the second integrated circuit; and coupling an external component to the double side molded interposer unit. | 07-02-2009 |
20090236718 | PACKAGE-ON-PACKAGE SYSTEM WITH INTERNAL STACKING MODULE INTERPOSER - A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors. | 09-24-2009 |
20100038781 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity. | 02-18-2010 |
20100237482 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LAYERED PACKAGING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace. | 09-23-2010 |
20110272807 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity. | 11-10-2011 |
Eun Joo Jung, Icheon-Si KR
Patent application number | Description | Published |
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20120156841 | METHOD OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates. | 06-21-2012 |
20140295641 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer. | 10-02-2014 |
Ha Chang Jung, Icheon-Si KR
Patent application number | Description | Published |
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20120087179 | MAGNETO-RESISTANCE ELEMENT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A magneto-resistance element is provided. The magneto-resistance element includes an underlying layer including a main metal selected from electrically conductive metals and an auxiliary metal selected from transition metals, a first magnetic layer stacked on the underlying layer, an insulation layer stacked on the first magnetic layer, and a second magnetic layer stacked on the insulation layer. | 04-12-2012 |
20130168862 | METHOD OF MANUFACTURING BARRIER LAYER PATTERNS OF A SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE OF BARRIER LAYER PATTERNS OF SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory and a structure of the semiconductor memory device, where the semiconductor memory device includes a material layer and a barrier layer. The barrier layer has a structure in which a horizontal cross-section of an upper portion thereof is larger than that of a lower portion thereof so that a fine pattern may be formed on the material layer using the barrier layer pattern without a structural damage or collapse in etching the underlying material layer. | 07-04-2013 |
20130313664 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device capable of minimizing operation current and a fabrication method thereof are provided. The resistive memory device includes an access device, a heating electrode formed on the access device and serving as a magnetoresistance device, and a variable resistance material formed on the heating electrode. | 11-28-2013 |
Hae Kang Jung, Icheon-Si KR
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20150280692 | DATA OUTPUT CIRCUIT OF A SEMICONDUCTOR APPARATUS - A data output circuit of a semiconductor apparatus includes a pull-up driver including a plurality of leg units configured to be controlled in respective resistance values in response to code signals, be controlled in an entire resistance value as one or more of the plurality of leg units are selectively activated in response to selection signals, and configured to apply an output voltage with an output voltage level selected according to a control of the entire resistance value among a plurality of output voltage levels, to a data output pad; a control block configured to generate the selection signals in response to mode register signals; and a code generator configured to generate the code signals according to an external resistor. | 10-01-2015 |
Hoe Kwon Jung, Icheon-Si KR
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20130162329 | ANTI-FUSE CIRCUIT AND FUSE REPTURE METHOD THEREOF - An anti-fuse circuit includes a control block configured to generate a first control signal and a second control signal in response to a first test signal and a second test signal, and a fuse set block configured to perform a primary fuse rupture operation in response to the first control signal and to perform a secondary fuse rupture operation in response to the second control signal, the fuse set block activating a fuse signal if any one of the primary fuse rupture operation and the secondary fuse rupture operation succeeds. | 06-27-2013 |
20130169349 | ANTI-FUSE CIRCUIT - An anti-fuse circuit includes: a first fuse unit including a first anti-fuse which is determined to be short-circuited if the first anti-fuse in a programmed state and determined not to be short-circuited if the first anti-fuse in a non-programmed state, and configured to generate an output signal according to a state of the anti-fuse and a restoration signal; and a second fuse unit including a second anti-fuse, and configured to activate the restoration signal when the second anti-fuse is in the programmed state in case where the first anti-fuse is in the programmed state. | 07-04-2013 |
Hoon Jung, Icheon-Si KR
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20130322023 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEATSINK CAP AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; molding an encapsulation directly on the integrated circuit and the substrate; forming a trench in the encapsulation having a trench bottom surface and surrounding the integrated circuit; and mounting a heatsink having a heatsink rim over the integrated circuit with the heatsink rim within the trench and the heatsink electrically isolated from the substrate. | 12-05-2013 |
Hun Sam Jung, Icheon-Si KR
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20090051397 | Clock pulse generating circuit - A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator. | 02-26-2009 |
20100109737 | Clock pulse generating circuit - A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator. | 05-06-2010 |
Inhwa Jung, Icheon-Si KR
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20150185758 | RECEIVER CIRCUIT FOR CORRECTING SKEW, SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING THE SAME - A receiver circuit includes a deserialization unit, a sampling clock control unit and a sampling clock generation unit. The deserialization unit is configured to receive sampling clock signals, sample a plurality of input data signals, and generate a plurality of internal data signals. The sampling clock control unit is configured to generate a delay control signal and a synchronization completion signal in response to the plurality of internal data signals and a first group of clock signals. The sampling clock generation unit delays the first group of clock signals and provides the delayed first group of clock signals as the sampling clock signals in response to the delay control signal, and provides a second group of clock signals having a phase leading by a predetermined amount with respect to the first group of clock signals, as the sampling clock signals in response to the synchronization completion signal. | 07-02-2015 |
Jin Ho Jung, Icheon-Si KR
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20130194561 | OPTICAL COMPONENT FOR MASKLESS EXPOSURE APPARATUS - Disclosed relates to an optical component for a maskless exposure apparatus, and more particularly, to a micro-prism array or a micro-mirror array which is an optical component capable of screening diffused light such that the image of a pixel of a digital micro-mirror display (DMD) formed by a first image-forming lens in the maskless exposure apparatus has no influence on the image of a neighboring pixel and of totally reflecting the light after reflection or diffraction at the same time, thus improving exposure performance by using the quantity of light being transmitted without a loss and increasing numerical apertures (NAs) at the same time. | 08-01-2013 |
Jong Ho Jung, Icheon-Si KR
Patent application number | Description | Published |
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20140002129 | ON-DIE TERMINATION CIRCUIT | 01-02-2014 |
20140003185 | ON-DIE TERMINATION CIRCUIT AND TERMINATION METHOD | 01-02-2014 |
20140055162 | ON-DIE TERMINATION CIRCUIT - An on-die termination circuit includes an impedance control unit configured to generate impedance control signals in response to an operation control signal, a driving unit configured to perform a termination function for a pad with an impedance controlled in response to the impedance control signals, and a termination control unit configured to deactivate the termination function of the driving unit in response to the operation control signal. | 02-27-2014 |
20140055183 | DOMAIN CROSSING CIRCUIT OF SEMICONDUCTOR APPARATUS - A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal. | 02-27-2014 |
20140286111 | DOMAIN CROSSING CIRCUIT OF SEMICONDUCTOR APPARATUS - A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal. | 09-25-2014 |
20150280720 | OUTPUT CONTROL CIRCUIT FOR SEMICONDUCTOR APPARATUS AND OUTPUT DRIVING CIRCUIT INCLUDING THE SAME - An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal. | 10-01-2015 |
Sang-Hun Jung, Icheon-Si KR
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20120199835 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - The present invention relates to a thin film transistor array panel and a manufacturing method thereof, and a thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a first conductive layer disposed on the substrate; a second conductive layer overlapping at least a portion of the edge of the first conductive layer on the first conductive layer and including a first portion overlapping the first conductive layer and a second portion not overlapping the first conductive layer; a first insulating layer disposed on the second conductive layer and having a contact hole exposing at least a portion of a boundary between the first portion and the second portion; and a third conductive layer disposed on the first insulating layer and simultaneously contacting the first portion and the second portion that are exposed through the contact hole. | 08-09-2012 |
20140009707 | DISPLAY APPARATUS HAVING IMPROVED STATIC DISCHARGE CHARACTERISTICS - A display apparatus includes a first substrate including a plurality of pixels, a second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. Each pixel includes a gate electrode, a gate insulating layer, a semiconductor pattern, a source electrode, a drain electrode, a first electrode, and a second electrode. The first electrode includes a first portion overlapping the drain electrode and a second portion outside the first portion, and the second electrode does not overlap the first portion of the first electrode. The first electrode or the second electrode is formed as a single unitary structure. | 01-09-2014 |
Sung Hyun Jung, Icheon-Si KR
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20140003159 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE HAVING THE SAME | 01-02-2014 |
20140003167 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE HAVING THE SAME | 01-02-2014 |
Sung Wook Jung, Icheon-Si KR
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20150092495 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array configured to store data; peripheral circuits configured to perform program verifying operation, read operation, and erase verifying operation on the memory cell array; and a control circuit configured to control the peripheral circuits, wherein the control circuit is configured to control the peripheral circuits to set a bit line voltage in the program verifying operation to have a higher level than a bit line voltage in the read operation, and a bit line voltage in the erase verifying operation to have a lower level than the bit line voltage in the read operation. | 04-02-2015 |
Sun-Hwa Jung, Icheon-Si KR
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20090218696 | SEMICONDUCTOR DEVICE INCLUDING A PADDING UNIT - A semiconductor device includes bit lines formed over a substrate and a padding unit formed over the bit lines. The padding unit includes stacked padding layers. A lower padding layer is formed between the bit lines and an upper padding layer. The upper layer as a slit formed therein. The lower padding layer prevents damage to the bit lines due to plasma gas entering through the slit. | 09-03-2009 |
Yong Soon Jung, Icheon-Si KR
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20090221126 | Method of Fabricating Capacitor of Semiconductor Device - Disclosed herein is a method of fabricating a capacitor of a semiconductor device that includes sequentially forming an interlayer insulating film defining a contact plug, a lower electrode oxide film, and a hard mask film over a semiconductor substrate; etching the hard mask film with a mask comprising a dummy pattern and a cell pattern to form a hard mask pattern wherein a first trench is formed in a dummy pattern region and a second trench is formed in a cell pattern region; forming a capping film that buries the first trench; and etching the lower electrode oxide film with the capping film and the hard mask pattern as a mask to form a lower electrode trench that exposes the contact plug. | 09-03-2009 |
Young Il Jung, Icheon-Si KR
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20140173184 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A method of operating a data storage device includes setting program verify voltages for verifying whether memory cells of a nonvolatile memory device are programmed to desired program states; transmitting the set program verify voltages to the nonvolatile memory device; generating data patterns respectively corresponding to program states based on the program verify voltages; transmitting a data pattern corresponding to the program verify voltages to the nonvolatile memory device; and programming the memory cells with the transmitted data pattern. | 06-19-2014 |