Patent application number | Description | Published |
20090001540 | Stackable Package by Using Internal Stacking Modules - A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical contact with the first semiconductor die through a first adhesive, such as a film on wire adhesive. A second DSM ISM is in physical contact with the first DSM ISM through a second adhesive. The arrangement of the first and second DSM ISM reduce headroom requirements for the package and increase device packing density. Each DSM ISM has semiconductor die disposed in cavities. An interposer is disposed above the top DSM ISM. Wire bonds connect the semiconductor die and DSM ISMs to the solder balls. An encapsulant surrounds the first semiconductor die and first DSM ISM with an exposed mold area in the encapsulant above the interposer. | 01-01-2009 |
20110024890 | Stackable Package By Using Internal Stacking Modules - A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate. | 02-03-2011 |
20140319702 | Stackable Package by Using Internal Stacking Modules - A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate. | 10-30-2014 |
Patent application number | Description | Published |
20100207262 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings. | 08-19-2010 |
20100237482 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LAYERED PACKAGING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace. | 09-23-2010 |
20110147906 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated interconnect pad; attaching an embedded interconnect to the plated interconnect pad; and forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side and the plated interconnect pad and the adhesive exposed from the encapsulation second side. | 06-23-2011 |
20110254172 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant. | 10-20-2011 |
Patent application number | Description | Published |
20130075933 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant. | 03-28-2013 |
20130105963 | Semiconductor Device and Method of Forming Thermal Interface Material and Heat Spreader Over Semiconductor Die | 05-02-2013 |
20130113118 | Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer - A semiconductor device has a semiconductor die with bumps formed over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate and conductive layer. A masking layer having an opaque portion and linear gradient contrast portion is formed over the patterning layer. The linear gradient contrast portion transitions from near transparent to near opaque. The patterning layer is exposed to ultraviolet light through the masking layer. The masking layer is removed and a portion of the patterning layer is removed to form an opening having a sloped surface to expose the conductive layer. The sloped surface in patterning layer can be formed by laser direct ablation. The semiconductor die is mounted to the substrate with the bumps electrically connected to the conductive layer and physically separated from the patterning layer. | 05-09-2013 |
20130154078 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SLUG AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation. | 06-20-2013 |
20130299995 | Semiconductor Device and Method of Depositing Underfill Material With Uniform Flow Rate - A semiconductor device has a substrate and insulating layer formed over a surface of the substrate. A first conductive layer is formed over the surface of the substrate. A second conductive layer is formed over an opposing surface of the substrate. A conductive via is formed through the substrate. An opening is formed in the insulating layer while leaving the first conductive layer intact. The opening narrows with a non-linear side or linear side. The opening can have a rectangular shape. A semiconductor die is mounted over the surface of the substrate. An underfill material is deposited between the semiconductor die and substrate. The opening in the insulating layer reduces a flow rate of the underfill material proximate to the opening. The flow rate of the underfill material proximate to the opening is substantially equal to a flow rate of the underfill material away from the opening. | 11-14-2013 |
20130300004 | Semiconductor Device and Method of Controlling Warpage in Semiconductor Package - A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel. | 11-14-2013 |
20130320519 | Semiconductor Device and Method of Backgrinding and Singulation of Semiconductor Wafer while Reducing Kerf Shifting and Protecting Wafer Surfaces - A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and into the trench. A lamination tape is applied over the protective coating. A portion of a second surface of the semiconductor wafer is removed by backgrinding or wafer thinning to expose the protecting coating in the trench. A die attach film is applied over the second surface of the semiconductor wafer. A cut or modified region is formed in the die attach film under the trench using a laser. The semiconductor wafer is expanded to separate the cut or modified region of the die attach film and singulate the semiconductor wafer. | 12-05-2013 |
20130322023 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEATSINK CAP AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; molding an encapsulation directly on the integrated circuit and the substrate; forming a trench in the encapsulation having a trench bottom surface and surrounding the integrated circuit; and mounting a heatsink having a heatsink rim over the integrated circuit with the heatsink rim within the trench and the heatsink electrically isolated from the substrate. | 12-05-2013 |
20130328220 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSIST AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming an integrated circuit device having a shaped side; mounting the integrated circuit device on the substrate; forming an encapsulation on the substrate and the integrate circuit device with the shaped side partially exposed from the encapsulation. | 12-12-2013 |
20130334714 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTION MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding. | 12-19-2013 |