Patent application number | Description | Published |
20090166757 | STRESS ENGINEERING FOR SRAM STABILITY - A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at least one SRAM cell with a gamma ratio of about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC, there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides a design structure of an IC embodied in a machine readable medium, the IC comprising at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET. | 07-02-2009 |
20100289088 | THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER - An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above. | 11-18-2010 |
20130134545 | SELF-LIMITING OXYGEN SEAL FOR HIGH-K DIELECTRIC, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region. | 05-30-2013 |
20150270828 | ESTABLISHING A THERMAL PROFILE ACROSS A SEMICONDUCTOR CHIP - Embodiments of the present invention disclose a semiconductor structure and method for establishing a thermal profile across a semiconductor chip. In certain embodiments, the semiconductor structure comprises a through-silicon via formed in a first semiconductor chip having thermal control circuitry, wherein the through-silicon via is formed in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, and wherein the through-silicon via conducts heat from the thermal control circuitry to the region. In other embodiments, the method comprises forming a through-silicon via in a first semiconductor chip having thermal control circuitry. The method also comprises forming the through-silicon via in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, wherein the through-silicon via conducts heat from the thermal control circuitry to the region. | 09-24-2015 |
Patent application number | Description | Published |
20120273894 | HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATOR INTERFACE - An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator. | 11-01-2012 |
20150129898 | IN-SITU ANNEALING FOR EXTENDING THE LIFETIME OF CMOS PRODUCTS - Methods for packaging a functional chip, methods for annealing a functional chip, and chip assemblies. A functional chip and an annealing chip are located inside a package. The functional chip includes an integrated circuit. The annealing chip includes an annealing element source comprised of an annealing element or a light source configured to emit electromagnetic radiation. The integrated circuit of the functional chip receives the annealing element, electromagnetic radiation, or both from the annealing chip in order to perform an annealing procedure that extends the useful lifetime of the packaged integrated circuit. | 05-14-2015 |
20150132862 | IN-SITU RELAXATION FOR IMPROVED CMOS PRODUCT LIFETIME - Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation. | 05-14-2015 |
Patent application number | Description | Published |
20100211247 | SYSTEM FOR PRODUCING AN ADAPTIVE DRIVING STRATEGY BASED ON EMISSION OPTIMIZATION - The system includes a road scenario sensor, a vehicle control unit, and a computer processing unit. The road scenario sensor detects upcoming road scenarios for the system vehicle. The computer processing unit receives an input from the road scenario sensor and determines a upcoming driving event based upon the detected upcoming road scenarios. The computer processing unit compares the upcoming driving event with an ideal emissions model having acceptable emission thresholds to determine an adaptive driving strategy. The adaptive driving strategy configures the system vehicle to reduce emissions for the upcoming upcoming driving event. The adaptive driving strategy optionally includes an optimal acceleration rate and/or an optimal power management strategy. The optimal acceleration rate is based upon the required speed of the vehicle at the upcoming driving event and the distance from the vehicle to the upcoming driving event, and the ideal emissions model having acceptable emission thresholds. | 08-19-2010 |
20120206252 | LANE DEPARTURE WARNING SYSTEM - Devices, methods and systems are disclosed herein to describe a lane departure warning system that warns the driver that the vehicle is about to leave a current lane and enter an adjacent lane. The driver of the vehicle is identified, and a corresponding profile is accessed. The driver's pupils may be measured and compared to pupil size data stored in the accessed profile. If the difference in pupil size exceeds a certain threshold, then the vehicle may activate a passive lane departure detector that warns the driver each time the vehicle is getting too close to an adjacent lane, thus alerting the driver that the vehicle may be unintentionally drifting into the next lane. Additional driving tendencies, such as steering angles and braking force, may also be used to determine whether the driver may benefit from lane departure assistance and whether to trigger activation of the lane departure detector. | 08-16-2012 |
20130335213 | LANE DEPARTURE WARNING/ASSISTANCE METHOD AND SYSTEM HAVING A THRESHOLD ADJUSTED BASED ON DRIVER IMPAIRMENT DETERMINATION USING PUPIL SIZE AND DRIVING PATTERNS - A method/system for lane departure warning/assistance that warns the driver that the vehicle is about to leave a current lane and enter an adjacent lane. The driver is identified, and a corresponding profile is accessed. The driver's pupils may be measured and compared to pupil size baseline data stored in the accessed profile. If the difference in pupil size exceeds a pupil size baseline by more than a deviation level, the method/system may adjust a lane departure warning/assistance threshold of a lane departure detector that warns the driver each time the vehicle is getting too close to an adjacent lane, thus alerting the driver that the vehicle may drift into the next lane. Driving patterns, such as steering angles and braking force, may also be used to adjust the lane departure warning/assistance threshold and determine whether the driver may benefit from lane departure warning/assistance. | 12-19-2013 |
20150086077 | SYSTEM AND METHOD OF ALERTING A DRIVER THAT VISUAL PERCEPTION OF PEDESTRIAN MAY BE DIFFICULT - A pedestrian perception alert system configured to issue a warning during real-time when a driver's visual detection of a pedestrian is difficult, and a method thereof is provided. The system includes a video camera, an alert for issuing a warning, a processor, and a Pedestrian Detection Unit (“PDU”). The PDU analyzes the video camera image to detect a pedestrian. A Global Clutter Analysis Unit (“GCAU”) generates a global clutter score. A Local Pedestrian Clutter Analysis Unit (“LPCAU”) generates a local pedestrian clutter score. The processer processes the global clutter score and local pedestrian clutter score so as to generate a pedestrian detection score. The alert is actuated when the pedestrian detection score is outside of a predetermined threshold so as to notify the driver that perception of a pedestrian is difficult at that time. | 03-26-2015 |
20150188233 | ARTIFICIAL SKIN FOR RADAR MANNEQUINS - An artificial skin for use on a radar mannequin exposed to electromagnetic radiation having a predetermined frequency and a radar mannequin having the artificial skin are provided. The artificial skin and the radar mannequin with the artificial skin are configured to produce a radar cross section that closely approximates the radar cross section of a human. The artificial skin includes a conductive layer of material and a shielding layer of material. The conductive layer and the shielding layer are configured to reflect electromagnetic radiation at a level of an electromagnetic response of human skin exposed to the electromagnetic radiation. The shielding layer also electromagnetically shields an inside surface of the artificial skin from electromagnetic radiation. | 07-02-2015 |