Patent application number | Description | Published |
20090166738 | RAM CELL INCLUDING A TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE EXTENSIONS - In a floating body storage transistor, the dopant concentration at the emitter side of the parasitic bipolar transistor may be significantly increased on the basis of a tilted implantation process, while maintaining a desired graded dopant profile at the collector side. Consequently, voltages for reading and writing of the FB storage transistor may be reduced, thereby also reducing the amount of die area consumed by respective boost converters. In addition, reliability of the FB transistor, as well as the retention time, may be increased. | 07-02-2009 |
20090242996 | SOI TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE REGIONS - By laterally asymmetrically defining the well dopant concentration in a floating body storage transistor, an increased well dopant concentration may be provided at the drain side, while a moderately low concentration may remain in the rest of the floating body region. Consequently, compared to conventional symmetric designs, a reduction in the read/write voltages for switching on the parasitic bipolar transistor may be accomplished, while the increased punch-through immunity may allow further scaling of the gate length of the floating body storage transistor. | 10-01-2009 |
20120329220 | Method of Improving Memory Cell Device by Ion Implantation - Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer. | 12-27-2012 |
20140078817 | INTEGRATED CIRCUITS WITH SRAM CELLS HAVING ADDITIONAL READ STACKS AND METHODS FOR THEIR FABRICATION - Integrated circuits that include SRAM cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of SRAM cells in and on a semiconductor substrate, each of the plurality of SRAM cells including a read pull down transistor and a read pass gate transistor. First conductivity-determining impurity ions are implanted to establish a first threshold voltage in each of the read pull down transistors; and second conductivity-determining impurity ions are implanted to establish a second threshold voltage different than the first threshold voltage in each of the read pass gate transistors. | 03-20-2014 |
20150060983 | SEMICONDUCTOR STRUCTURE INCLUDING A SPLIT GATE NONVOLATILE MEMORY CELL AND A HIGH VOLTAGE TRANSISTOR, AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal. | 03-05-2015 |
20150078068 | INTEGRATED CIRCUITS WITH SRAM CELLS HAVING ADDITIONAL READ STACKS - Integrated circuits that include SRAM cells having additional read stacks are provided. In accordance with one embodiment an integrated circuit includes a memory storage array of memory cells. The integrated circuit includes a read stack coupled to each memory cell of the memory storage array. Each read stack includes a read pull-down transistor having a first threshold voltage, and a read pass gate transistor coupled in series with the read pull down transistor and having a second threshold voltage greater than the first threshold voltage. | 03-19-2015 |
20160035856 | SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF - An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor. | 02-04-2016 |
20160064228 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC MATERIAL AND SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR - An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region. | 03-03-2016 |