Patent application number | Description | Published |
20090166676 | SIGE DEVICE WITH SIGE-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT - A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe. | 07-02-2009 |
20090236637 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer. | 09-24-2009 |
20090261937 | INTEGRATED INDUCTOR - An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well. | 10-22-2009 |
20100001412 | BOND PAD STRUCTURE - A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad. | 01-07-2010 |
20100044833 | INTEGRATED CAPACITOR - According to the preferred embodiment, an integrated capacitor having a comb-meander structure is provided. The integrated capacitor comprises a first comb-shaped metal pattern; a second comb-shaped metal pattern interdigitating with the first comb-shaped metal pattern; and a meandering metal pattern traversing a spacing between the first and second comb-shaped metal patterns. | 02-25-2010 |
20100059867 | INTEGRATED CIRCUIT CHIP WITH SEAL RING STRUCTURE - An integrated circuit chip includes an analog and/or RF circuit block, a digital circuit, and a seal ring structure surrounding and protecting the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring, and a discontinuous inner seal ring divided into at least a first portion and a second portion. The second portion is situated in front of the analog and/or RF circuit block for shielding a noise from interfering the analog and/or RF circuit block. | 03-11-2010 |
20100061026 | ESD PROTECTION CIRCUIT AND METHOD THEREOF - An Electrostatic Discharge protection circuit, the circuit includes a transient detecting circuit, a level adjusting circuit, a discharging circuit, and a sustaining circuit. The transient detecting circuit is coupled to a first pad for detecting an input signal at the first pad to generate a transient signal; the level adjusting circuit is coupled to the transient detecting circuit for adjusting an output voltage at an output terminal of the level adjusting circuit; the discharging circuit is coupled to the first pad and the output terminal of the level adjusting circuit for discharging the input signal of the first pad to a second pad when enabled by the output voltage; and the sustaining circuit is coupled between the level adjusting circuit and the transient detecting circuit, for selectively controlling the level adjusting circuit to sustain an enablement of the discharging circuit according to the transient signal. | 03-11-2010 |
20100065943 | METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF - A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor. | 03-18-2010 |
20100102421 | INTEGRATED CIRCUIT CHIP WITH SEAL RING STRUCTURE - An integrated circuit chip includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and an inner seal ring, wherein the inner seal ring comprises a gap that is situated in front of the analog and/or RF circuit block. | 04-29-2010 |
20100164018 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR DEVICE - A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region. | 07-01-2010 |
20100193925 | LEADFRAME FOR SEMICONDUCTOR PACKAGES - A leadframe for semiconductor packages. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. Each lead has a corresponding lead relative to a predetermined center line. A predetermined pair of corresponding leads are substantial asymmetrical with each other in appearance relative to the predetermined center line. | 08-05-2010 |
20100252860 | LATERAL BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE - A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region. | 10-07-2010 |
20100289119 | INTEGRATED CAPACITOR - According to the preferred embodiment, an integrated capacitor having a key-shaped structure is provided. The integrated capacitor comprises a first pair of key-shaped metal patterns and a second pair of key-shaped metal patterns. The first pair of key-shaped metal patterns engages with the second pair of key-shaped metal patterns, and a dielectric layer is situated therebetween. | 11-18-2010 |
20110001168 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer. | 01-06-2011 |
20120038055 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first power/ground mesh wiring lines, in a second conductive layer overlying the first Insulating layer, for distributing power signal or ground signal; and a second insulating layer covering the second conductive layer and the first insulating layer. | 02-16-2012 |
20120043663 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer. | 02-23-2012 |
20120168862 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR DEVICE - A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region. | 07-05-2012 |
20140097012 | LEADFRAME FOR SEMICONDUCTOR PACKAGES - A leadframe for semiconductor packages is provided. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. The leads includes a first lead and a second lead being at opposite locations of the leadframe relative to a center line through the die pad. The first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values. The plurality of leads are disconnected to each other. | 04-10-2014 |
20140175608 | METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF - A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. | 06-26-2014 |