Patent application number | Description | Published |
20110062547 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film. | 03-17-2011 |
20110095380 | SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below. | 04-28-2011 |
20110128301 | ELECTRONIC MAGNIFIER - A purpose of the invention is to provide an electronic magnifier that can facilitate grasping of a position when a display portion is moved in a magnified display state and can improve the visibility. An image capturing section | 06-02-2011 |
20130134549 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film. | 05-30-2013 |
Patent application number | Description | Published |
20110064971 | GLASS SUBSTRATE MANUFACTURING METHOD, GLASS SUBSTRATE POLISHING METHOD, GLASS SUBSTRATE POLISHING APPARATUS AND GLASS SUBSTRATE - A polishing apparatus, includes: a motor; and a controlling unit configured to control the motor, wherein: a glass substrate is polished by causing the controlling unit to control a driving of the motor; and the controlling unit executes a controlling operation for controlling a polishing of the glass substrate, based on an electric power or an electric energy required for the driving of the motor. | 03-17-2011 |
20110192132 | FIBER COMPOSITE TWISTED CABLE - The invention relates to a composite twisted cable formed by impregnating carbon fibers with thermoplastic resin, and provides a fiber composite twisted cable which allows downsizing of a reel by being easy to be bent, can be transported to mountain areas which is normally hard to achieve a transport with a large vehicle, is hard to be curled, and is superior in workability. It is a cable having 1×n structure which is formed by impregnating bundles of carbon fibers with thermosetting resin, then twisting a plurality of strands each formed by covering an outer periphery of the bundle with a fiber, and then curing the thermosetting resin by applying the heat treatment, and a core strand and side strands which constitute the cable are separated and independent without being bonded so as to allow independent behavior of the respective strands when the cable is bent. | 08-11-2011 |
20140212974 | CELL CULTURE MEMBRANE, CELL CULTURE SUBSTRATE, AND METHOD FOR MANUFACTURING CELL CULTURE SUBSTRATE - Provided is: a cell culture membrane, which is free from materials derived from living organisms, can easily be industrially mass-produced, exhibits superior long-term storage properties and chemical resistance, has excellent cell adhesion properties and long-term culture properties and is capable of replicating a cell adhesion morphology that is similar to that of collagen derived from living organisms and being used for conventional cell cultivation. Also provided are a cell culture substrate, and a method for manufacturing the cell culture substrate. In the present invention, as a cell adhesion layer, a polymer membrane represented by formula (I) is formed on the base of a cell culture substrate so as to have a membrane thickness equal to or greater than 0.2 μm (in the formula, R1 and R2 represent a —(CH | 07-31-2014 |
20150033213 | COMPILING METHOD, STORAGE MEDIUM AND COMPILING APPARATUS - A compiling method for reading, by a computer comprising a processor and a memory, a source file therein and outputting an executable binary file, the compiling method including: a first step of receiving, by the computer, an interface file including a process and a module constructing a business process, input/output information of data of the business process being defined in the interface file, operation information for data set to be used in the business process being defined in the interface file; a second step of validating, by the computer, the operation information for the data set defined in the interface file; a third step of inhibiting, by the computer, generation of the executable binary file when a validation result is invalid; and a fourth step of generating, by the computer, the executable binary file from a source file containing the interface file when the validation result is valid. | 01-29-2015 |
20150240188 | LIQUID DETERGENT - This liquid detergent contains an α-sulfofatty acid ester salt (component (a)), an alkylbenzene sulfonate (component (b)), a polyoxyethylene alkyl ether sulfate (component (c)), and an alkanolamine (component (d)). The amount of the component (a) is 5% by mass or greater; the total amount of the component (b) and the component (c) is 5% by mass or greater; the total amount of the component (a), the component (b), and the component (c) is 10% by mass to 50% by mass, the mass ratio represented by (d)/(a) is 1/5 or greater, and the mass ratio represented by (a)/((b)+(c)) is 1 or less. | 08-27-2015 |
Patent application number | Description | Published |
20090108832 | HIGH FREQUENCY POWER DETECTOR CIRCUIT AND RADIO COMMUNICATION DEVICE - First and second envelope detector circuits have, respectively, a resistance row, a capacitative element connected to the resistance row in parallel and a transistor connected between a connection point between the resistance row and the capacitative element and a predetermined voltage node. An output of a level shifter is supplied to a gate or a base of the transistor of the first envelope detector circuit. A predetermined voltage is supplied to a gate or a base of the transistor of the second envelope detector circuit. A detector detects an intermediate terminal voltage of the resistance row of the first envelope detector circuit with reference to a total voltage or an intermediate terminal voltage of the resistance row of the second envelope detector circuit. | 04-30-2009 |
20090135866 | OPTICAL TRANSMISSION CIRCUIT - An optical transmission circuit includes a light emitting device ( | 05-28-2009 |
20090166513 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device in the present invention includes pixels, arranged in a matrix, each of which converts light into a signal voltage; column signal lines each of which is provided for corresponding one of columns, so that the signal voltage is provided to corresponding one of the column signal lines; and AD converting units each of which is provided for the corresponding one of the column signal lines, and configured to convert the signal voltage into a digital signal, wherein each of the AD converting units includes: a comparing unit generating an output signal indicating a greater voltage of the signal voltage and a reference voltage; and a counting unit counting a count value until logic of the output signal is inverted, and the solid-state imaging device further includes a suspending unit suspending power supply to the comparing units after the logic of the output signals is inverted. | 07-02-2009 |
20100226411 | LOW-NOISE AMPLIFIER AND RADIO COMMUNICATION SYSTEM - Power consumption of an amplification circuit ( | 09-09-2010 |
20100271248 | RAMP WAVE OUTPUT CIRCUIT, ANALOG/DIGITAL CONVERSION CIRCUIT, AND CAMERA - A ramp wave output circuit includes a ramp wave generation circuit generating a ramp wave, and a low-pass filter having a variable cutoff frequency, which receives the ramp wave. The low-pass filter operates at a first cutoff frequency for a predetermined time period after the receipt of the ramp wave, and at a second cutoff frequency, which is larger than the first cutoff frequency, after the predetermined time period has passed. | 10-28-2010 |
20100289936 | BUFFER CIRCUIT, IMAGE SENSOR CHIP COMPRISING THE SAME, AND IMAGE PICKUP DEVICE - A buffer circuit includes: first and second cascode constant current sources ( | 11-18-2010 |
20110317051 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a plurality of pixels, which convert light into signal voltages, and a plurality of analog-digital (AD) converters, which convert the signal voltages into a plurality of digital signals. Each of the plurality of AD converters includes an analog circuit, which receives a same power as a power of the plurality of pixels, and a digital circuit, which receives power having a voltage lower than a voltage of the analog circuit. The solid-state imaging device further includes a controller configured to suspend supplying the same power to the analog circuit, which is included in one of the plurality of AD converters that has finished a conversion. | 12-29-2011 |
Patent application number | Description | Published |
20100252438 | CARBON FIBER STRAND AND PROCESS FOR PRODUCING THE SAME - A carbon fiber strand which is produced by obtaining a solidified-yarn strand by spinning with a spinneret having 20,000-30,000 spinning holes, passing the strand through an interlacing nozzle having an air blowing pressure of 20-60 kPa to obtain precursor fibers, oxidizing them in heated air having a temperature of 200-280° C. to obtain oxidized fibers, subjecting these oxidized fibers to a first carbonization treatment in an inert-gas atmosphere at a temperature of 300-900° C. in which the fibers are firstly stretched in a stretch ratio of 1.03-1.06 and then secondarily stretched in a stretch ratio of 0.9-1.01, subsequently conducting a second carbonization treatment in an inert-gas atmosphere at 1,360-2,100° C., and then conducting a surface oxidization treatment in an aqueous solution of an inorganic acid salt in a quantity of electricity of 20-100 C per g of the carbon fibers. This carbon fiber strand has a strand tensile strength of 5,650 MPa or higher, strand tensile modulus of 300 GPa or higher, and strand width of 5.5 mm or larger. No strand crack is observed in an examination by a strand crack evaluation method. | 10-07-2010 |
20100252439 | CARBON FIBER STRAND AND PROCESS FOR PRODUCING THE SAME - A carbon fiber strand obtained by bundling 20,000-30,000 carbon fibers each having, in the surface thereof, creases which are parallel to the fiber-axis direction. In an examination with a scanning probe microscope, the creases in the carbon fiber surface are apart from each other at a distance of 120-160 nm and have a depth of 12-23 nm, excluding 23 nm. The carbon fibers have an average fiber diameter of 4.5-6.5 nm, specific surface area of 0.9-2.3 m | 10-07-2010 |
Patent application number | Description | Published |
20130039407 | LOW-POWER DOWN-SAMPLED FLOATING TAP DECISION FEEDBACK EQUALIZATION - In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained IT resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with IT resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms. | 02-14-2013 |
20130114665 | Low Nonlinear Distortion Variable Gain Amplifier - A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain. | 05-09-2013 |
20130230093 | SHIFT REGISTER BASED DOWNSAMPLED FLOATING TAP DECISION FEEDBACK EQUALIZATION - Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal. | 09-05-2013 |
20140028416 | Low-Voltage Active Inductor - An active inductor circuit includes a field-effect transistor having a first source/drain adapted for connection with a first voltage source, a capacitor coupled between the first voltage source and a gate of the field-effect transistor, a resistor coupled between a second source/drain of the field-effect transistor and the gate of the field-effect transistor, and a current source coupled with the gate of the field-effect transistor. A voltage headroom of the active inductor circuit is controlled as a function of at least one of a magnitude of current generated by the current source and a resistance of the resistor. | 01-30-2014 |
20140169426 | RECEIVER WITH DISTORTION COMPENSATION CIRCUIT - A receiver containing analog circuitry that generates distortion, a distortion compensation circuit coupled to an output of the analog circuitry, and a slicer, operating as a signal peak detector, coupled to the distortion compensation circuitry. The distortion compensation circuit has a subtractor, a function generator, and a weighting circuit. The subtractor has a first input coupled to the output of the analog circuitry, a second input, and an output. The function generator has an input coupled to the first input of the subtractor. The weighting circuit, responsive to a weighting coefficient, is coupled between an output of the function circuit and the second input of the first subtractor. The function generator has a transfer function with a third-power term and the weighting coefficient is set to a value based on the level of the signal peaks that will least partially reduce distortion in signals on the output of the subtractor. | 06-19-2014 |