Patent application number | Description | Published |
20100073051 | LOW JITTER LARGE FREQUENCY TUNING LC PLL FOR MULTI-SPEED CLOCKING APPLICATIONS - ABSTRACT The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range. | 03-25-2010 |
20130076450 | LOW NOISE BIAS CIRCUIT FOR A PLL OSCILLATOR - A system, method, and apparatus for generating a low noise bias current to improve jitter performance in a wide frequency range LC-based phase-locked loop (PLL) circuit for multi-speed clocking applications. A plurality of noise-reducing stages are coupled in series and disposed between a power supply and a voltage controlled oscillator (VCO) including: a first stage VCO regulator; and a second stage bias circuit having a plurality of PMOS transistors cascode-coupled to each other and optionally grouped into one or more parallel branches of cascode-coupled transistor pairs. Each branch can be automatically enabled by a calibration code based on the desired reference clock signal in order to provide a wide range of currents to the voltage controlled oscillator. The cascode coupled pair includes a bias transistor coupled in series with a self-biased current buffer to provide high output impedance with minimal current change for any input voltage change from noise. | 03-28-2013 |
20130169314 | METHODS AND CIRCUITS FOR ADJUSTING PARAMETERS OF A TRANSCEIVER - Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold. | 07-04-2013 |
20150326229 | Phase Interpolator with Phase Traversing for Delay-Locked Loop - A system, method and computer readable storage medium are disclosed for phase interpolator to generate a single phase output clock signal based on plurality of phase-shifted component clock signals and a digital user input control signal to be utilized in combination with a delay-locked loop circuit. In one embodiment, the phase interpolator utilizes a method of phase-traversing when generating the single phase output clock signal that prevents over- or undershooting of the desired target phase of the single phase output clock signal. | 11-12-2015 |
Patent application number | Description | Published |
20130153149 | Substrate Processing Tool with Tunable Fluid Flow - Embodiments provided herein describe substrate processing tools. The substrate processing tools include a housing defining a processing chamber. A substrate support is coupled to the housing and configured to support a substrate within the processing chamber. The substrate has a central axis. A first annular member is moveably coupled to the housing and positioned within the processing chamber. The first annular member circumscribes the central axis of the substrate. A second annular member is moveably coupled to the housing and positioned within the processing chamber. The second annular member circumscribes the central axis of the substrate. Movement of the first annular member and the second annular member relative to the housing changes a flow of processing fluid through the processing chamber. | 06-20-2013 |
20130153536 | COMBINATORIAL PROCESSING USING A REMOTE PLASMA SOURCE - Methods and apparatuses for combinatorial processing using a remote plasma source are disclosed. The apparatus includes a remote plasma source and an inner chamber enclosing a substrate support. An aperture is operable to provide plasma exposure to a site-isolated region on a substrate. A transport system moves the substrate support and is capable of positioning the substrate such that the site-isolated region can be located anywhere on the substrate. Barriers and a gas purge system operate to provide site-isolation. Plasma exposure parameters can be varied in a combinatorial manner. Such parameters include source gases for the plasma generator, plasma filtering parameters, exposure time, gas flow rate, frequency, plasma generator power, plasma generation method, chamber pressure, substrate temperature, distance between plasma source and substrate, substrate bias voltage, or combinations thereof. | 06-20-2013 |
20130156937 | System and Method for Aligning Sputter Sources - Embodiments provided herein describe systems and methods for aligning sputtering sources, such as in a substrate processing tool. The substrate processing tool includes at least one sputtering source and a device. Each of sputtering sources includes a target having a central axis. The device has an axis and is detachably coupled to the at least one sputtering source. The device indicates to a user a direction in which the central axis of the target of the at least one sputtering source is oriented. | 06-20-2013 |
20140124359 | New Magnet Design Which Improves Erosion Profile for PVD Systems - Methods and apparatuses for performing combinatorial processing are disclosed. Methods include introducing a substrate into a processing chamber. The processing chamber includes a sputter assembly disposed over the substrate. The sputter assembly includes a rotatable n-fold, symmetric-shaped magnetron and a sputter target. The methods include depositing a first film on the surface of a first site-isolated region of the substrate. The methods further include depositing a second film on the surface of a second site-isolated region of the substrate. Furthermore, methods include evaluating results of the first and second films. | 05-08-2014 |
20140166840 | Substrate Carrier - A substrate carrier is provided. The substrate carrier includes a base for supporting a substrate. A plurality of support tabs is affixed to a surface of the base. The plurality of support tabs have a cavity defined within an inner region of each support tab of the plurality of support tabs. A plurality of protrusions extends from the surface of the base, wherein one of the plurality of protrusions mates with one cavity to support one of the plurality of support tabs. A film is deposited over the surface of the base, surfaces of the plurality of support tabs and surfaces of the plurality of protrusions. | 06-19-2014 |
20140174918 | Sputter Gun - A sputter gun is provided. The sputter gun includes a target and a first plate coupled to a surface of the target. A first magnet is disposed over a second magnet. A second plate coupled to a surface of the first magnet and a gap is defined between a surface of the second magnet and a surface of the first plate. A fluid inlet and a fluid outlet are disposed above a surface of the first magnet. A restriction bar is coupled to the second plate, wherein the restriction bar is configured to prevent a flow path of fluid through the first inlet to the second inlet unless the fluid traverses the gap defined between a surface of the second magnet and a surface of the first plate. Alternative configurations of the sputter gun are included. | 06-26-2014 |
Patent application number | Description | Published |
20090164982 | METHOD AND SYSTEM FOR TRANSFORMING BINARIES TO USE DIFFERENT INSTRUCTIONS - In general, in one aspect, the invention relates to a method for transforming binaries to use different instructions. The method includes identifying an instruction in the binary, where the instruction is an unimplemented instruction of an instruction set of a processor. The method further includes replacing the instruction with emulation code, where execution of the emulation code emulates execution of the instruction, and generating an updated binary including the emulation code. | 06-25-2009 |
20090241098 | LINK-TIME REDUNDANT CODE ELIMINATION USING FUNCTIONAL EQUIVALENCE - Duplicative code found in modules of high level computer code can be eliminated at link-time. A compiler forms a plurality of object files from a software program in which each object file includes one or more functions associated with the software program. An analyzer examines each function to ascertain whether any of the plurality of object files include functional duplicates. In addition, call and caller routing references are determined for each of the object files and functions contained therein. Responsive to determining that a functional equivalence exists, the routing of duplicative functions is altered to reference a golden copy of the same function. Once the call and caller information has been re-routed, the duplicative function(s) is(are) deleted. | 09-24-2009 |
20100125837 | REDUNDANT EXCEPTION HANDLING CODE REMOVAL - A system performs operations comprising creating a call graph for a program translated from source code, identifying redundant exception handling code in the program utilizing the call graph, and removing the redundant exception handling code. The operation of identifying redundant exception handling code may comprise identifying at least one function or callsite by determining that a first function in the at least one function's or callsite's callee chain throws an exception and that the exception is handled by a second function in the function's or callsite's callee chain or by determining that an exception is not thrown in the at least one function's or callsite's callee chain. The operation of removing the redundant exception handling code may comprise removing redundant exception handling code included in at least one function or callsite and/or removing at least one entry for the at least one function or callsite from an exception lookup table. | 05-20-2010 |
20100146220 | EFFICIENT PROGRAM INSTRUMENTATION FOR MEMORY PROFILING - A system and method for performing efficient program instrumentation for memory profiling. A computing system comprises a memory profiler comprising a static binary instrumentation (SBI) tool and a dynamic binary analysis (DBA) tool. The profiler is configured to selectively instrument memory access operations of a software application. Instrumentation may be bypassed completely for an instruction if the instruction satisfies some predetermined conditions. Some sample conditions include the instruction accesses an address within a predetermined read-only area, the instruction accesses an address within a user-specified address range, and/or the instruction is a load instruction accessing a memory location determined from a data flow graph to store an initialized value. An instrumented memory access instruction may have memory checking analysis performed only upon an initial execution of the instruction in response to determining during initial execution that a read data value of the instruction is initialized. Both unnecessary instrumentation and memory checking analysis may be reduced. | 06-10-2010 |
20110010696 | DUPLICATE VIRTUAL FUNCTION TABLE REMOVAL - One or more embodiments of the present invention relate to a method for duplicate virtual function table removal. The method includes identifying, using a processor of a computer, a first virtual function table formed when a first source code is compiled into a first object code. The method further includes using the processor, identifying a second virtual function table formed when a second source code is compiled into a second object code. The method further includes, independent of linking the first object code to a first executable binary code and the second object code to a second executable binary code, identifying, using the processor, that the first virtual function table and the second virtual function table are identical and, using the processor, deleting the second virtual function table. | 01-13-2011 |
Patent application number | Description | Published |
20080196833 | RETAINING RING WITH SHAPED SURFACE - A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions. | 08-21-2008 |
20080254722 | PAD CONDITIONER - A pad conditioner is provided for conditioning a polishing pad in chemical mechanical planarization (CMP). The pad conditioner comprises a plastic abrasive portion having a first hardness and optionally a brush portion having a second hardness less than the first hardness. The plastic abrasive portion comprises a base plate and a plurality of plastic nodules formed on a surface of the base plate, each of the plastic nodules having a planar top surface, wherein the planar top surface is positioned to substantially contact a polishing pad. The brush portion may be positioned adjacent to the plastic abrasive portion, the brush portion having a plurality of brush elements positioned to substantially contact the pad. | 10-16-2008 |
20110195639 | RETAINING RING WITH SHAPED SURFACE - A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions. | 08-11-2011 |
20120071067 | RETAINING RING WITH SHAPED SURFACE - A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions. | 03-22-2012 |
20120276817 | EDDY CURRENT MONITORING OF METAL RESIDUE OR METAL PILLARS - A method of chemical mechanical polishing a substrate includes polishing a metal layer on the substrate at a polishing station, monitoring thickness of the metal layer during polishing at the polishing station with an eddy current monitoring system, and halting polishing when the eddy current monitoring system indicates that residue of the metal layer is removed from an underlying layer and a top surface of the underlying layer is exposed. | 11-01-2012 |
20140030956 | CONTROL OF POLISHING OF MULTIPLE SUBSTRATES ON THE SAME PLATEN IN CHEMICAL MECHANICAL POLISHING - A polishing method includes positioning two substrates in contact with the same polishing pad. Prior to commencement of polishing and while the two substrates are in contact with the polishing pad, two starting values are generated from an in-situ monitoring system. Either a starting polishing time or a pressure applied to one of the substrates can be adjusted so that the two substrates have closer endpoint conditions. During polishing the two substrates are monitored with the in-situ monitoring system to generate a two sequences of values, and a polishing endpoint can be detected or an adjustment for a polishing parameter can be based on the two sequences of values. | 01-30-2014 |
20140053981 | Retaining Ring With Shaped Surface - A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions. | 02-27-2014 |
Patent application number | Description | Published |
20080240100 | LAYER THREE SATELLITE FUNCTIONALITY IN A DATA NETWORK - Method and system for providing access layer satellite architecture in a data network including receiving a data packet from an access layer network device, the data packet including a Virtual Local Area Network (VLAN) identifier associated with a port on the access layer network device, performing a route lookup procedure based on the received data packet to determine a destination of the data packet, updating an ARP table with a Media Access Control (MAC) address associated with the VLAN identifier and the port of the received data packet, and transmitting the data packet to a destination network device, is disclosed. | 10-02-2008 |
20090213867 | BLADE ROUTER WITH NAT SUPPORT - A blade router for increased interface scalability is provided. The blade router may address interface scalability by having each of the linecards manage its interfaces locally and may use the concept of virtual and local interfaces for intelligent forwarding. The blade router may appear as a single router from the customer perspective during configuration. For some embodiments, two virtual interfaces may be used, one for regular interface traffic and another for Network Address Translation (NAT)-enabled interface traffic. | 08-27-2009 |
20090213869 | BLADE SWITCH - A blade switch for increased interface scalability is provided. The blade switch may address interface scalability by having each of the switch linecards manage its interfaces locally and may use the concept of virtual and local interfaces for intelligent forwarding. The blade switch may appear as a single network switch having a single bridge ID from the network perspective during operation and from the customer perspective during configuration. | 08-27-2009 |
20110134923 | Intelligent Adjunct Network Device - An adjunct network device includes several ports, an uplink interface, and an adjunct forwarding engine coupled to the ports and the uplink interface. A first port is configured to receive a packet, which includes a destination address. The adjunct forwarding engine is configured to send the packet to the uplink interface if the destination address is not associated with any of the ports. The packet is sent to one of the ports if the destination address is associated with the one of the ports. | 06-09-2011 |
20110200041 | Intelligent Adjunct Network Device - An adjunct network device includes several ports, an uplink interface, and an adjunct forwarding engine coupled to the ports and the uplink interface. A first port is configured to receive a packet, which includes a destination address. The adjunct forwarding engine is configured to send the packet to the uplink interface if the destination address is not associated with any of the ports. The packet is sent to one of the ports if the destination address is associated with the one of the ports. | 08-18-2011 |
20130262703 | SYSTEM AND METHOD FOR REDUCING NETFLOW TRAFFIC IN A NETWORK ENVIRONMENT - A an example method includes building a dictionary between an exporter and a collector by encoding a first data record of a flow according to a dictionary template and exporting the first data record to the collector via a network communication. The method can also include compressing a second data record of the flow using the dictionary, where the compressing comprises encoding the second data record according to an encoding template; and exporting the second data record to the collector to be decompressed using the dictionary. | 10-03-2013 |
20150195218 | Interface Bundles In Virtual Network Devices - A virtual network device includes several different virtual network device sub-units, which collectively operate as a single logical network device. An interface bundle includes interfaces in more than one of the different virtual network device sub-units included in the virtual network device. The interface bundle is coupled to a virtual link bundle, which connects the virtual network device to another device. The interface bundle is managed as a single logical interface. | 07-09-2015 |
Patent application number | Description | Published |
20100327905 | Method and Apparatus for Providing a Non-Volatile Programmable Transistor - A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function. | 12-30-2010 |
20110221472 | Method and Apparatus for Providing A Non-Volatile Programmable Transistor - A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function. | 09-15-2011 |
Patent application number | Description | Published |
20110078427 | TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT - A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment. | 03-31-2011 |
20130124838 | INSTRUCTION LEVEL EXECUTION PREEMPTION - One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity. | 05-16-2013 |
20130145102 | MULTI-LEVEL INSTRUCTION CACHE PREFETCHING - One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache | 06-06-2013 |
20140165072 | TECHNIQUE FOR SAVING AND RESTORING THREAD GROUP OPERATING STATE - A streaming multiprocessor (SM) included within a parallel processing unit (PPU) is configured to suspend a thread group executing on the SM and to save the operating state of the suspended thread group. A load-store unit (LSU) within the SM re-maps local memory associated with the thread group to a location in global memory. Subsequently, the SM may re-launch the suspended thread group. The LSU may then perform local memory access operations on behalf of the re-launched thread group with the re-mapped local memory that resides in global memory. | 06-12-2014 |
20140189260 | APPROACH FOR CONTEXT SWITCHING OF LOCK-BIT PROTECTED MEMORY - A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming multiprocessor refuses the request. Otherwise, the streaming multiprocessor asserts the address lock, asserts a thread group lock in a plurality of thread group locks, where the thread group lock is associated with the thread group, and grants the request. One advantage of the disclosed techniques is that acquired locks are released when a thread is preempted. As a result, a preempted thread that has previously acquired a lock does not retain the lock indefinitely. | 07-03-2014 |
20140189329 | COOPERATIVE THREAD ARRAY GRANULARITY CONTEXT SWITCH DURING TRAP HANDLING - Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors. | 07-03-2014 |
20140189711 | COOPERATIVE THREAD ARRAY GRANULARITY CONTEXT SWITCH DURING TRAP HANDLING - Techniques are provided for restoring thread groups in a cooperative thread array (CTA) within a processing core. Each thread group in the CTA is launched to execute a context restore routine. Each thread group, executes the context restore routine to restore from a memory a first portion of context associated with the thread group, and determines whether the thread group completed an assigned function prior to executing the context restore routine. If the thread group completed an assigned function prior to executing the context restore routine, then the thread group exits the context restore routine. If the thread group did not complete the assigned function prior to executing the context restore routine, then the thread group executes one or more operations associated with a trap handler routine. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors. | 07-03-2014 |
20140337389 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SCHEDULING TASKS ASSOCIATED WITH CONTINUATION THREAD BLOCKS - A system, method, and computer program product for scheduling tasks associated with continuation thread blocks. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor. | 11-13-2014 |
20140337569 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR LOW LATENCY SCHEDULING AND LAUNCH OF MEMORY DEFINED TASKS - A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task metadata data structure to be stored in a memory associated with a processor, transmitting the task metadata data structure to a scheduling unit of the processor, storing the task metadata data structure in a cache unit included in the scheduling unit, and copying the task metadata data structure from the cache unit to the memory. | 11-13-2014 |
20140372703 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR WARMING A CACHE FOR A TASK LAUNCH - A system, method, and computer program product for warming a cache for a task launch is described. The method includes the steps of receiving a task data structure that defines a processing task, extracting information stored in a cache warming field of the task data structure, and, prior to executing the processing task, generating a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory. | 12-18-2014 |
Patent application number | Description | Published |
20090281534 | SYSTEM FOR DELIVERING THERAPY - The system of the preferred embodiments includes a first rotational element, a second rotational element, and a therapeutic source coupled to the rotational elements. The system permits simultaneous attachment to and movement around a surface of tissue, preferably during an ablation procedure (either during lesion creation or between lesion creation events), or during any other suitable procedure. The therapeutic source functions to translate along the path of tissue and deliver therapy as the first and second rotational elements rotate and roll along the path of tissue. The therapeutic source preferably delivers contiguous doses of therapy along the path of tissue. The system is preferably designed for delivering therapy to tissue and, more specifically, for delivering therapy to cardiac tissue. The system, however, may be alternatively used in any suitable environment and for any suitable reason. | 11-12-2009 |
20100036208 | METHOD AND APPARATUS FOR IN-VIVO PHYSIOLOGICAL MONITORING - A method is provided that includes providing a monitoring apparatus including one or more modules within a target cavity or lumen of a body. The one or more modules are provided within the target cavity or lumen in a first state in which the monitoring apparatus is configured to remain within the target cavity or lumen. The method further includes monitoring physiological conditions of the body using one or more sensors within the one or more modules, and providing the one or more modules in a second state in which the monitoring apparatus is configured to exit the target cavity or lumen. | 02-11-2010 |
20130131665 | Transmural Ablation Device - A transmural ablation device is provided to achieve endocardial and epicardial ablation at the same site but directed from the inner and outer surfaces of the heart to create a transmural lesion. By ablating from both sides of the heart tissue, it is possible to increase the depth of the lesion created and to increase the likelihood of a transmural lesion. Embodiments pertain to techniques to align the endocardial and epicardial ablation elements and techniques to position and move the endocardial and epicardial ablation elements along a predefined linear, curvilinear, or circular path. The ability to bring the epicardial and endocardial elements more closely or firmly with the underlying tissue is important in creating optimal lesions. Magnetic force attracts the epicardial and endocardial elements. | 05-23-2013 |
20150099979 | VISUALIZATION OF HEART WALL TISSUE - Various aspects of the instant disclosure are directed to imaging tissue. As may be implemented in accordance with one or more embodiments, aspects of the present disclosure are directed to apparatuses and methods involving the following. A light source includes an array of light emitters that illuminate a tissue region of a heart wall with light at different wavelength ranges. A light collector collects multispectral images including respective images collected at each of the different wavelength ranges at which the tissue region is illuminated. A catheter positions the light source and light collector proximate the tissue region of the heart wall for respectively illuminating the tissue region and collecting the multispectral images. A display circuit collects and displays one or more images depicting a condition of the health of heart wall tissue, based on the respective images collected at the different ones of the wavelength ranges. | 04-09-2015 |
Patent application number | Description | Published |
20100303092 | Dynamically Configuring Attributes of a Parent Circuit on a Network Element - Methods and apparatus for dynamically configuring a parent circuit through a subscriber record on an authentication, authorization, and accounting (AAA) server responsive to an authorization event for the subscriber session on the network element. According to one embodiment of the invention, the AAA server accesses the subscriber record for a subscriber session on the network element. Based on this subscriber record, a set of one or more attributes for a subscriber circuit and a set of one or more attributes for a parent circuit of the subscriber circuit are determined The network element applies the set of subscriber circuit attributes to the subscriber circuit and the set of parent circuit attributes to the parent circuit. | 12-02-2010 |
20120300621 | DYNAMICALLY CONFIGURING ATTRIBUTES OF A PARENT CIRCUIT ON A NETWORK ELEMENT - Methods and apparatus for dynamically configuring a parent circuit through a subscriber record on an authentication, authorization, and accounting (AAA) server responsive to an authorization event for the subscriber session on the network element. According to one embodiment of the invention, the AAA server accesses the subscriber record for a subscriber session on the network element. Based on this subscriber record, a set of one or more attributes for a subscriber circuit and a set of one or more attributes for a parent circuit of the subscriber circuit are determined. The network element applies the set of subscriber circuit attributes to the subscriber circuit and the set of parent circuit attributes to the parent circuit. | 11-29-2012 |
20140133356 | DYNAMICALLY CONFIGURING ATTRIBUTES OF A PARENT CIRCUIT ON A NETWORK ELEMENT - Methods and apparatus for dynamically configuring a parent circuit through a subscriber record on an authentication, authorization, and accounting (AAA) server responsive to an authorization event for the subscriber session on the network element. According to one embodiment of the invention, the AAA server accesses the subscriber record for a subscriber session on the network element. Based on this subscriber record, a set of one or more attributes for a subscriber circuit and a set of one or more attributes for a parent circuit of the subscriber circuit are determined. The network element applies the set of subscriber circuit attributes to the subscriber circuit and the set of parent circuit attributes to the parent circuit. | 05-15-2014 |
Patent application number | Description | Published |
20080198427 | Multiple Lightguide Electronic Document Imaging Device - A multi-lightguide document imaging device is proposed for scanning a document transported atop it. The device includes:
| 08-21-2008 |
20090091648 | Multi-resolution Image Sensor Array with High Image Quality Pixel Readout Circuitry - A configurable, compact multi-resolution linear image sensor array is disclosed. The multi-resolution image sensor array employs a spatial array of photoelectric sites with each site having an image output terminal and a cluster of switched photo-detector elements. To effect a high quality snapshot operation mode for a high pixel count array, a transfer control switch is added bridging each photo-detector element and its correspondingly connected negative input terminal of an operational amplifier to form an active pixel sensor circuit. To minimize a reset kTC noise associated with numerous traditional active pixel sensor circuits, an in-pixel KTC noise-correlated correlated multiple sampling (CMS) circuitry is also proposed to replace an otherwise traditional correlated double sampling (CDS) circuitry. | 04-09-2009 |
20100007775 | Areal Active Pixel Image Sensor with Programmable Row-specific Gain for Hyper-Spectral Imaging - An areal active pixel image sensor (AAPS) with programmable row-specific gain is disclosed for converting hyper-spectral light image into video output signal (VOS). The AAPS includes:
| 01-14-2010 |
20100213355 | Full-width Line Image-sensing Head - A full-width line image-sensing head (FLIH) is proposed for, expressed in X-Y-Z coordinates, converting a pixel line image (PLI) of length L | 08-26-2010 |
20110019044 | Time Delay Integration Based MOS Photoelectric Pixel Sensing Circuit - A time delay integration (TDI) based MOS photoelectric pixel sensing circuit (TDIPSC) is proposed. The TDIPSC includes multi-element photoelectric pixel sensor (MEPS) having sub-pixel sensor elements SPSE | 01-27-2011 |
20110019046 | Wafer-scale Linear Image Sensor Chip and Method with Replicated Gapless Pixel Line and Signal Readout Circuit Segments - A wafer-scale linear image sensor chip (WLISC) is proposed with gapless pixel line and signal readout circuit segments. The WLISC converts pixel line image (PLI) of length L | 01-27-2011 |
20110149132 | Wafer-scale Cluster Image Sensor Chip and Method with Replicated Gapless Pixel Line and Signal Readout Circuit Segments - A multi-pixel row wafer-scale cluster image sensor chip (WCISC) is proposed. Expressed in X-Y-Z coordinates with its pixel rows along X-axis, the WCISC converts areal image frame (IMFM) into areal image frame signal (AIFS). The WCISC includes multiple imaging pixel rows PXRW | 06-23-2011 |
20130208110 | System and method for monitoring multiple targets using a single camera - Techniques to monitor multiple targets with a single camera are disclosed. In one embodiment, an image sensor is provided with two or more readout circuits, each operating independently and is designed to read out charges from a designated area of the image sensor. When two or more designated sensing areas in the image sensor are being focused onto different objects and read out respectively, such an image sensor is capable of monitoring multiple targets. When placed in traffic surveillance, a camera equipped with such an image sensor is able to monitor multiple forward and backward lanes in near or far field. Further with the control of the designated areas, different resolutions of the images may be produced. | 08-15-2013 |
20130208154 | High-sensitivity CMOS image sensors - Designs of image sensors with subpixels are disclosed. According to one aspect of an image sensor in one embodiment, subpixels within a pixel are designed without significantly increasing the cell or pixel area of the pixel. The readouts from the subpixels are accumulated to increase the sensitivity of the pixel without increasing the area of the image sensor. According to another aspect of the image sensors in the present invention, some subpixels within a pixel are respectively coated with filters, each designed for a frequency range. Thus the frequency response of a CMOS image sensor can be enhanced significantly according to application. | 08-15-2013 |
20140022425 | Multi-band sensors - Designs of multi-band sensor array to generate multi-spectral images are disclosed. According to one aspect of the present invention, a multi-band sensor array includes one linear sensor configured to sense a scene in panchromatic spectrum to produce a panchromatic (PAN) sensing signal, and four color-band linear sensors to sense the same scene in different color bands to produce respective sensing signals. These sensors are packaged in a single module that is disposed on a single optical plane when used to scan a scene. A multi-spectral image is produced by combining these sensing signals. Further a unique packaging of the sensor array and a combination of soft and hard PCB are disclosed to withstand extremes in a harsh environment. | 01-23-2014 |
Patent application number | Description | Published |
20080211570 | Systems, Methods, and Integrated Circuits with Inrush-Limited Power Islands - A new approach for managing turn-on of power islands uses a precharge phase to begin the process of bringing up the island's internal supply voltage, while minimizing transients and associated power-control-logic instability. | 09-04-2008 |
20080229121 | Selectively Powered Data Interfaces - A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits. | 09-18-2008 |
20090160423 | Self-configurable multi-regulator ASIC core power delivery - An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation. | 06-25-2009 |
20090164807 | Self-configurable multi-regulator ASIC core power delivery - A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation. | 06-25-2009 |
20130154593 | ADAPTIVE PHASE-LEAD COMPENSATION WITH MILLER EFFECT - An adaptive phase-lead compensation (zero) circuit is disclosed that can be added to a circuit (e.g., a CMOS-based LDO) to ease the compensation and increase the phase margin of the circuit. By using the disclosed adaptive phase-lead compensation circuit, an adjustable resistance can be connected to any nodes in the compensated circuit rather than just to the voltage source (VDD) or ground (GND), allowing the Miller Effect to be used via a Miller capacitor. | 06-20-2013 |
20140032956 | ULTRA-DEEP POWER-DOWN MODE FOR MEMORY DEVICES - A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down. | 01-30-2014 |
20150227155 | VOLTAGE REFERENCE WITH LOW SENSITIVTY TO PACKAGE SHIFT - In a bandgap voltage reference with low package shift, a proportional to absolute temperature (PTAT) voltage is generated using a single diode biased at two different current levels at two different times. Using the same diode for both current density measurements removes the absolute value of the base-emitter junction voltage (Vbe) and any package shift in the PTAT voltage. The bandgap voltage reference can be implemented in a single or differential circuit topology. In some implementations, the bandgap voltage reference can include circuitry for curvature correction. | 08-13-2015 |
20150241956 | ULTRA-DEEP POWER-DOWN MODE FOR MEMORY DEVICES - A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down. | 08-27-2015 |