Chi-Shun Weng
Chi-Shun Weng, Tainan Hsien TW
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20100272217 | Power Consumption Control Methods Applied to Communication Systems, and Related Devices - A power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a transmission distance between the communication system and another communication system. Another power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a signal index of the communication system. | 10-28-2010 |
Chi-Shun Weng, Anding Township TW
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20100085062 | Network Device, Network Connection Detector and Detection Method Thereof - A network device, a network connection detector and a detection method thereof are disclosed. The network device comprises a socket, a waveform generator and a reflected wave detector. The waveform generator sends a first test wave to at least a first contact of a plurality of contacts of a socket and then the reflected wave detector detects a first reflected wave that is corresponding to the first test wave and is reflected from the first contact. Thus a first control signal is generated according to detection result of the first reflected wave. | 04-08-2010 |
Chi-Shun Weng, Hsinchu TW
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20090259422 | Transmission Medium Testing Apparatus and Method - The invention provides a method for testing a transmission medium used in a full-duplex communication system comprising an endpoint that comprises a transmitting end (TX) and a receiving end (RX); the method comprises the steps of: first, transmitting a transmitted signal which comprises a test signal sequence with a high auto-correlation characteristic; then, receiving a received signal, and performing a correlation operation on the test signal and the received signal; finally, according to the result of the correlation operation, determining the impedance matching condition of the transmission medium. | 10-15-2009 |
20150035555 | CIRCUIT LIFETIME MEASURING DEVICE AND METHOD - The present invention discloses a circuit lifetime measuring device to estimate the rest lifetime of a target circuit, comprising: a reference clock receiving end for receiving a reference clock; a correlation signal generating circuit for providing a correlation signal in which at least some operating settings of the correlation signal generating circuit and the target circuit vary synchronously; a storage circuit for storing an initial relation between the reference clock and the correlation signal; a measuring circuit, coupled to the reference clock receiving end and the correlation signal generating circuit, for measuring a present relation between the reference clock and the correlation signal; and an estimating circuit, coupled to the storage circuit and the measuring circuit, for generating an estimation value according to the initial relation and the present relation, wherein the estimation value indicates the rest lifetime of the target circuit. | 02-05-2015 |
Chi-Shun Weng, Hsinchu County TW
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20090050904 | LIGHT EMITTING DIODE CIRCUIT - A light emitting diode circuit includes a chip and a light emitting diode. The chip includes a current control unit that is used for controlling a driving current flowing through a path. The light emitting diode is positioned outside of the chip and is coupled to the path. The light emitting diode generates a light source according to the driving current. The light emitting diode circuit can directly control the current value of a driving current flowing through the light emitting diode. In this way, the circuit design is simplified and the production cost of the electronic product is reduced. | 02-26-2009 |
20090175322 | TRANSCEIVER WITH ADJUSTABLE SAMPLING VALUES AND SIGNAL TRANSCEIVING METHOD THEREOF - A transceiver includes: a first DAC, for receiving a first digital signal to generate an analog signal; an operation circuit, coupled to the first DAC, for receiving the analog signal and a feedback signal to generate an operated analog signal; an ADC, for generating a second digital signal according to the operated analog signal; a digital signal processing circuit, for processing the second digital signal to generate a processed digital signal; a second DAC, for generating the feedback signal according to the processed digital signal; an adjustable delay circuit, for delaying a clock signal according to a control signal to adjust at least one sampling point of at least one of the first DAC, the second DAC and the ADC; and a control circuit, for generating the control signal according to the processed digital signal. | 07-09-2009 |
20090190631 | METHOD FOR GENERATING A SPREAD SPECTRUM CLOCK AND APPARATUS THEREOF - A method for generating a spread spectrum clock includes the steps of providing a reference clock having a reference period; generating a plurality of output clocks respectively having different phases according to the reference clock; generating a first/second control signal according to the reference clock and a spread spectrum clock and starting a first/second duration accordingly; during the first/second duration, outputting a first/second selecting signal representing a first/second predetermined sequence according to the first/second control signal, wherein the second predetermined sequence is a substantial reversed sequence of the first predetermined sequence; and during the first/second duration, sequentially outputting some or all of the output clocks as the spread spectrum clock according to the first/second predetermined sequence. | 07-30-2009 |
20090198754 | Order adaptive finite impulse response filter and operating method thereof - A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and an estimate unit. Depending on intensities of responses to interferences, at least one of the allocation FIR filters may be coupled in series to any one of the designated finite impulse response filters, thereby to provide a signal having excellent quality. | 08-06-2009 |
20120011217 | MASTER/SLAVE DECISION DEVICE AND MASTER/SLAVE DECISION METHOD APPLIED TO NETWORK DEVICE - A master/slave decision device applied to a first network device is provided, where the first network device is coupled to a second network device, and the master/slave decision device includes a seed distance detection unit and a decision unit. The seed distance decision unit is utilized for detecting a seed distance between a first seed utilized in a first scrambler of the first network device and a second seed utilized in a second scrambler of the second network device. The decision unit is coupled to the seed distance detecting unit, and is utilized for determining the first network device to be a master device or a slave device according to the seed distance. | 01-12-2012 |
20120137156 | CONTROLLING CIRCUIT WITH POWER SAVING MECHANISM AND ERRONEOUS WAKE-UP PREVENTING MECHANISM AND METHOD THEREOF - A controlling circuit supporting a power saving mechanism includes: a transmitting interface arranged to perform a signal transmission with a specific controlling circuit; and a setting unit coupled to the transmitting interface. The setting unit is arranged to control the specific controlling circuit to operate in the power saving mechanism. | 05-31-2012 |
Chi-Shun Weng, Hsin Chu County TW
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20090164628 | CIRCUIT AND METHOD FOR SETTING DATA AND THEIR APPLICATION TO INTEGRATED CIRCUIT - An integrated circuit is disclosed, including at least one configuration pin, an interface circuit, a detecting circuit, a determining circuit and a storage unit. A physical layer circuit of the invention not only increases the flexibility of setting PHY addresses, but also reduces the number of configuration pins. | 06-25-2009 |
Chi-Shun Weng, Zhubei City TW
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20120213306 | APPARATUS AND METHOD FOR CROSS CLOCK DOMAIN INTERFERENCE CANCELLATION - An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal. The cancellation signal generator adjusts the cancellation signal according to a phase difference between the interference signal and the cancellation signal. | 08-23-2012 |