Patent application number | Description | Published |
20110107032 | CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT - A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc. | 05-05-2011 |
20110173402 | HARDWARE SUPPORT FOR COLLECTING PERFORMANCE COUNTERS DIRECTLY TO MEMORY - Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element. | 07-14-2011 |
20110173403 | USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY - A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data. | 07-14-2011 |
20110173431 | HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST RECONFIGURATION OF PERFORMANCE COUNTERS - Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters. | 07-14-2011 |
20110173503 | HARDWARE ENABLED PERFORMANCE COUNTERS WITH SUPPORT FOR OPERATING SYSTEM CONTEXT SWITCHING - A device for supporting hardware enabled performance counters with support for context switching include a plurality of performance counters operable to collect information associated with one or more computer system related activities, a first register operable to store a memory address, a second register operable to store a mode indication, and a state machine operable to read the second register and cause the plurality of performance counters to copy the information to memory area indicated by the memory address based on the mode indication. | 07-14-2011 |
20110173588 | HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST MULTIPLEXING OF PERFORMANCE COUNTERS - Hardware support for software controlled fast multiplexing of performance counters may include a plurality of performance counters operable to collect one or more counts of one or more selected activities, and a plurality of registers operable to store a set of performance counter configurations. A state machine may be operable to automatically select a register from the plurality of registers for reconfiguring the one or more performance counters in response to receiving a first signal. The state machine may be further operable to reconfigure the one or more performance counters based on a configuration specified in the selected register. The state machine yet further may be operable to copy data in selected one or more of the plurality of performance counters to a memory location, or to copy data from the memory location to the counters, in response to receiving a second signal. The state machine may be operable to store or restore the counter values and state machine configuration in response to a context switch event. | 07-14-2011 |
20110219208 | MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER - A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency. | 09-08-2011 |
20120311316 | HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST RECONFIGURATION OF PERFORMANCE COUNTERS - Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters. | 12-06-2012 |
20130019086 | HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST MULTIPLEXING OF PERFORMANCE COUNTERS - Performance counters may be operable to collect one or more counts of one or more selected activities, and registers may be operable to store a set of performance counter configurations. A state machine may be operable to automatically select a register from the registers for reconfiguring the one or more performance counters in response to receiving a first signal. The state machine may be further operable to reconfigure the one or more performance counters based on a configuration specified in the selected register. The state machine yet further may be operable to copy data in selected one or more of the performance counters to a memory location, or to copy data from the memory location to the counters, in response to receiving a second signal. The state machine may be operable to store or restore the counter values and state machine configuration in response to a context switch event. | 01-17-2013 |
Patent application number | Description | Published |
20080229321 | QUALITY OF SERVICE SCHEDULING FOR SIMULTANEOUS MULTI-THREADED PROCESSORS - A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees. | 09-18-2008 |
20080263278 | CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT - A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc. | 10-23-2008 |
20080288957 | METHOD AND SYSTEM FOR OPTIMIZING COMMUNICATION IN MPI PROGRAMS FOR AN EXECUTION ENVIRONMENT - A system and method for mapping application tasks to processors in a computing environment that takes into account the hardware communication topology of a machine and an application communication pattern. The hardware communication topology (HCT) is defined according to hardware parameters affecting communication between two tasks, such as connectivity, bandwidth and latency; and, the application communication pattern (ACP) is defined to mean the number and size of bytes that are communicated between the different pairs of communicating tasks. By collecting information on the messages exchanged by the tasks that communicate, the communication pattern of the application may be determined. By combing the HCT and ACP a cost model for a given mapping can be determined. Any algorithm computing a mapping can use the HCT, ACP, and the cost model, thus the combination of an HCT, ACP, and cost model allow an automatically optimized mapping of tasks to processing elements to be achieved | 11-20-2008 |
20090178052 | LATENCY-AWARE THREAD SCHEDULING IN NON-UNIFORM CACHE ARCHITECTURE SYSTEMS - A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data. Information as to which banks store which data may also be provided, for example, by the hardware. This information may be used to schedule threads on one or more cores. A selected bank in cache memory may be reserved strictly for selected data. | 07-09-2009 |
20100250853 | Prefetch engine based translation prefetching - A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped. | 09-30-2010 |
20100281218 | INTELLIGENT CACHE REPLACEMENT MECHANISM WITH VARYING AND ADAPTIVE TEMPORAL RESIDENCY REQUIREMENTS - A method for replacing cached data is disclosed. The method in one aspect associates an importance value to each block of data in the cache. When a new entry needs to be stored in the cache, a cache block for replacing is selected based on the importance values associated with cache blocks. In another aspect, the importance values are set according to the hardware and/or software's knowledge of the memory access patterns. The method in one aspect may also include varying the importance value over time over different processing requirements. | 11-04-2010 |
20110126200 | Scheduling for functional units on simultaneous multi-threaded processors - A method and system for scheduling threads on simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system determines thread scheduling based on the information. | 05-26-2011 |
20110161597 | Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller - A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a storage controller is configured to receive a memory access request including a real address from a processor, determine whether the real address is for the first logical partition or for the second logical partition. If the address is for the first logical partition the storage controller communicates with an IO controller in the storage memory to service the memory access request. If the address is for the direct memory region, the memory controller services the memory access request in a conventional manner. | 06-30-2011 |
20110246582 | Message Passing with Queues and Channels - In an embodiment, a send thread receives an identifier that identifies a destination node and a pointer to data. The send thread creates a first send request in response to the receipt of the identifier and the data pointer. The send thread selects a selected channel from among a plurality of channels. The selected channel comprises a selected hand-off queue and an identification of a selected message unit. Each of the channels identifies a different message unit. The selected hand-off queue is randomly accessible. If the selected hand-off queue contains an available entry, the send thread adds the first send request to the selected hand-off queue. If the selected hand-off queue does not contain an available entry, the send thread removes a second send request from the selected hand-off queue and sends the second send request to the selected message unit. | 10-06-2011 |
20120023300 | MEMORY PAGE MANAGEMENT IN A TIERED MEMORY SYSTEM - Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key. | 01-26-2012 |
20120066473 | Memory Architecture with Policy Based Data Storage - A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved. | 03-15-2012 |
20120124298 | LOCAL SYNCHRONIZATION IN A MEMORY HIERARCHY - A method, system, and computer usable program product for local synchronization in a memory hierarchy in a multi-core data processing system are provided in the illustrative embodiments. A request to acquire a reservation for a reservation granule is received at a first core. The reservation is acquired in a first local cache associated with the first core in response to a cache line including the reservation granule being present and writable in the first local cache. A conditional store request to store at the reservation granule is received at the first core. A determination is made whether the reservation remains held at the first local cache. The store operation is performed at the first local cache responsive to reservation remaining held at the first local cache. | 05-17-2012 |
20120179879 | MECHANISMS FOR EFFICIENT INTRA-DIE/INTRA-CHIP COLLECTIVE MESSAGING - Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains. | 07-12-2012 |
20120179896 | METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM - A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed. | 07-12-2012 |
20120185672 | LOCAL-ONLY SYNCHRONIZING OPERATIONS - Performing a series of successive synchronizing operations by a core on data shared by a plurality of cores may include a first core indicating an upcoming synchronizing operation on shared data. A second memory layer stores the shared data and tracks the first core's ownership of the shared data. The second memory layer is shared via coherency operations among the first core and one or more second cores. The first core may perform one or more synchronization operations on the shared data without requiring interaction from the second memory layer. | 07-19-2012 |
20120198118 | USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY - A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data. | 08-02-2012 |
20120204065 | METHOD FOR GUARANTEEING PROGRAM CORRECTNESS USING FINE-GRAINED HARDWARE SPECULATIVE EXECUTION - A method for checking program correctness may include executing a program on a main hardware thread in speculative execution mode on a hardware execution context on a chip having a plurality of hardware execution contexts. In this mode, the main hardware thread's state is not committed to main memory. Correctness checks by a plurality of helper threads are executed in parallel to the main hardware thread. Each helper thread runs on a separate hardware execution context on the chip in parallel with the main hardware thread. The correctness checks determine a safe point in the program up to which the operations executed by said main hardware thread are correct. Once the main hardware thread reaches the safe point, the mode of execution of the main hardware thread is switched to non-speculative. The runtime then causes the main thread to re-enter speculative mode of execution. | 08-09-2012 |
20130007378 | MECHANISMS FOR EFFICIENT INTRA-DIE/INTRA-CHIP COLLECTIVE MESSAGING - Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains. | 01-03-2013 |
20130013891 | METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM - A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed. | 01-10-2013 |
20130263121 | METHOD TO EMBED A LIGHT-WEIGHT KERNEL IN A FULL-WEIGHT KERNEL TO PROVIDE A HETEROGENEOUS EXECUTION ENVIRONMENT - Enabling a Light-Weight Kernel (LWK) to run in a virtualized environment on a Full-Weight Kernel (FWK), in one aspect, may include replacing a FWK loader, e.g., FWK's dynamic library loader or linker, with a LWK library on a first computing entity for an application allocated to run on one or more second computing entities. The LWK library may be enabled to initialize the one or more second computing entities and associated memory allocated to run the application under the LWK library. The LWK library may be enabled to manage the one or more second computing entities and said associated memory and resources needed by the application. | 10-03-2013 |
20130263157 | METHOD TO UTILIZE CORES IN DIFFERENT OPERATING SYSTEM PARTITIONS - A system call utility may be provided on a first operating system managing a first hardware computing entity. The system call utility may take as an argument a pointer to a computer code a second operating system established to run on the first hardware computing entity. The first operating system is enabled to execute the computer code natively on the first hardware computing entity, and return a result of the computer code executed on the first hardware computing entity to the second operating system. | 10-03-2013 |
20130317873 | MEETING ATTENDANCE PLANNER - A system and method for planning meeting attendance. The method includes receiving from a meeting requestor a request to schedule a proposed meeting at a time interval. The method also includes automatically calculating by a computer processor an attendance probability value for a potential attendee based, at least in part, on the potential attendee's location over time. The method further includes marking an electronic calendar of the meeting requestor with an indicia of the attendance probability value for the potential attendee. Additionally, the method may include automatically scheduling the proposed meeting if the attendance probability value is beyond an attendance probability threshold. | 11-28-2013 |
20130317874 | MEETING ATTENDANCE PLANNER - A system for planning meeting attendance. The system includes a computer processor configured to receive from a meeting requestor a request to schedule a proposed meeting at a time interval. The computer processor is further configured to calculate an attendance probability value for a potential attendee based, at least in part, on the potential attendee's location over time. Additionally, the computer processor is configured to mark an electronic calendar of the meeting requestor with an indicia of the attendance probability value for the potential attendee. The computer processor may also be configured to automatically schedule the proposed meeting if the attendance probability value is beyond an attendance probability threshold. | 11-28-2013 |
20130326180 | MECHANISM FOR OPTIMIZED INTRA-DIE INTER-NODELET MESSAGING COMMUNICATION - Point-to-point intra-nodelet messaging support for nodelets on a single chip that obey MPI semantics may be provided. In one aspect, a local buffering mechanism is employed that obeys standard communication protocols for the network communications between the nodelets integrated in a single chip. Sending messages from one nodelet to another nodelet on the same chip may be performed not via the network, but by exchanging messages in the point-to-point messaging buckets between the nodelets. The messaging buckets need not be part of the memory system of the nodelets. Specialized hardware controllers may be used for moving data between the nodelets and each messaging bucket, and ensuring correct operation of the network protocol. | 12-05-2013 |
20140123027 | VIRTUAL MEETINGS - A method for managing virtual meetings includes initiating participation with a first user interface in a first meeting, initiating participation with the first user interface in a second meeting, determining whether attention of a user is directed towards the first meeting or the second meeting, and configuring the user interface such that the user interacts with meeting resources associated with the first meeting responsive to determining that the attention of the user is directed towards the first meeting. | 05-01-2014 |
20140123030 | VIRTUAL MEETINGS - A system for managing virtual meetings includes a processor operative to initiate participation with a first user interface in a first meeting, initiate participation with the first user interface in a second meeting, determining whether attention of a user is directed towards the first meeting or the second meeting, and configure the user interface such that the user interacts with meeting resources associated with the first meeting responsive to determining that the attention of the user is directed towards the first meeting. | 05-01-2014 |
20140180512 | LOCATION-BASED VEHICLE POWERTRAIN REGULATION SYSTEM - A vehicle control system to control operation of a vehicle includes a powertrain system operable according to a plurality of operating modes that drive the vehicle. A sensor is mounted to the vehicle to detect a quality of air surrounding the vehicle. A vehicle control module is configured to select an operating mode of the powertrain system. The operating mode is selected to reduce at least one emission exhausted from the vehicle that contributes to a low air quality measure by the sensor. | 06-26-2014 |
20140180513 | LOCATION-BASED VEHICLE POWERTRAIN REGULATION SYSTEM - A vehicle control system to control operation of a vehicle includes a powertrain system operable according to a plurality of operating modes that drive the vehicle. A sensor is mounted to the vehicle to detect a quality of air surrounding the vehicle. A vehicle control module is configured to select an operating mode of the powertrain system. The operating mode is selected to reduce at least one emission exhausted from the vehicle that contributes to a low air quality measure by the sensor. | 06-26-2014 |
20140380196 | Creation and Prioritization of Multiple Virtual Universe Teleports in Response to an Event - Useful work or services can be automated or otherwise facilitated or solutions to real world events developed by emulation of a real-world environment (which can contain objects representing virtual objects) with a virtual environment and generating a prioritized sequence of locations and associated tasks in accordance with resources related to the event in a virtual universe. Performance of the prioritized tasks at the prioritized locations is facilitated in the virtual universe by locally generating teleportation invitations corresponding to locations in the ordered sequence of locations. | 12-25-2014 |
20150019126 | PROVIDING NAVIGATIONAL SUPPORT THROUGH CORRECTIVE DATA - A method and system for providing navigational support through corrective data includes monitoring a user's current position and travel pattern. A likelihood that the user is lost may be calculated based on the user's travel pattern and current position. If the likelihood exceeds a threshold value, the user may be provided with corrective data such as photographs or landmark information through visual or audio communication to assist the user in taking a corrective action or preventing getting lost. | 01-15-2015 |
Patent application number | Description | Published |
20090081204 | SYNTHETIC IMMUNOGENIC BUT NON-AMYLOIDOGENIC PEPTIDES HOMOLOGOUS TO AMYLOID BETA FOR INDUCTION OF AN IMMUNE RESPONSE TO AMYLOID BETA AND AMYLOID DEPOSITS - The present invention relates to synthetic immunogenic but non-amyloidogenic peptides homologous to amyloid β which can be used alone or conjugated to an immunostimulatory molecule in an immunizing composition for inducing an immune response to amyloid β peptides and amyloid deposits. | 03-26-2009 |
20090163420 | SYNTHETIC IMMUNOGENIC BUT NON-DEPOSIT-FORMING POLYPEPTIDES AND PEPTIDES HOMOLOGOUS TO AMYLOID BETA, PRION PROTEIN, AMYLIN, ALPHA-SYNUCLEIN, OR POLYGLUTAMINE REPEATS FOR INDUCTION OF AN IMMUNE RESPONSE THERETO - The present invention relates to immunogenic but non-depositing-forming polypeptides or peptides homologous to amyloid β, prion, amylin or α-synuclein which can be used alone or conjugated to an immunostimulatory molecule in an immunizing composition for inducing an immune response to amyloid β peptides and amyloid deposits, to prion protein and prion deposits, to amylin and amylin deposits, to α-synuclein and deposits containing α-synuclein, or to polyglutamine repeats and deposits of proteins containing polyglutamine repeats. Described are also antibodies directed against such peptides, their generation, and their use in methods of passive immunization to such peptides and deposits. | 06-25-2009 |
20090175853 | METHOD FOR TREATING AMYLOID DISEASE - Disclosed herein are methods for treating amyloid disease in humans by clearing amyloid peptides from one or more bodily fluids such as, e.g. blood, of a patient. In particular, the methods are based on the administration of compounds capable of binding to amyloid-beta (Aβ) or on dialysis of blood or plasma exchange in order to remove Aβ peptides from the blood circulation, and/or brain or other affected organs. | 07-09-2009 |
20100279340 | Imaging agents for protein misfolding - Charged and neutral small fluorescent molecules based upon the styryl scaffold are useful as imaging agents for misfolded proteins such as amyloid plaque. Charged molecules are prepared using pyrrolidine catalyzed reactions by solution-phase synthesis. Neutral styryl molecules are prepared using acetic anhydride catalyzed reactions, Horner-Emmons reactions or Wittig reactions. | 11-04-2010 |
20110060035 | PREVENTING AND TREATING AMYLOID-BETA DEPOSITION BY STIMULATION OF INNATE IMMUNITY - The present invention is directed to a method of preventing or reducing amyloid deposition in a subject. This method involves selecting a subject with amyloid deposits and stimulating the innate immune system of the selected subject under conditions effective to reduce the amyloid deposits. Also disclosed is a method of preventing or treating cerebral amyloidosis and Alzheimer's Disease in a subject by administering to the selected subject an agent that stimulates the innate immune system. In addition, a composition useful for the stimulation of the innate immune system of a subject exhibiting symptoms associated with amyloid deposition is disclosed. | 03-10-2011 |
20130022630 | METHOD FOR TREATING AMYLOID DISEASE - The invention relates to methods for treating human amyloid disease by administration of modified Aβ peptide immunogens. | 01-24-2013 |
20130045216 | Method for Treating Amyloid Disease - Disclosed herein are methods for treating amyloid disease in humans by clearing amyloid peptides from one or more bodily fluids such as, e.g., blood, of a patient. In particular, the methods are based on the administration of compounds capable of binding to amyloid-beta (Aβ) or on dialysis of blood or plasma exchange in order to remove Aβ peptides from the blood circulation, and/or brain or other affected organs. | 02-21-2013 |
20150044243 | MUCOSAL IMMUNIZATION TO PREVENT PRION INFECTION - Vaccines against prion disease eliciting a humoral immune response when administered mucosally are described. The vaccines comprise a prion protein, a prion protein fragment, or a non-amyloidogenic prion protein homolog and an adjuvant suitable for inducing a humoral immune response after mucosal administration. Suitable adjuvants include cholera toxin subunit B, heat-labile enterotoxin and aluminum hydroxide. Alternatively, the vaccine comprises a vector encoding a prion protein, fragment, or homolog in an attenuated | 02-12-2015 |