Patent application number | Description | Published |
20090085072 | Biosensor using nanoscale material as transistor channel and method of fabricating the same - Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time. | 04-02-2009 |
20090162998 | Methods of Manufacturing Memory Units, and Methods of Manufacturing Semiconductor Devices - Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided. | 06-25-2009 |
20090189152 | FERROELECTRIC MEMORY DEVICE - Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode. | 07-30-2009 |
20090209071 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - First nanowires and second nanowires are alternately disposed and spaced apart on a first substrate in a second direction that is parallel to an adjacent major surface of the first substrate. Each of the first and second nanowires extends in a first direction that is perpendicular to the second direction, and the first and second nanowires are doped with first and second conductive types, respectively. A plurality of gate lines are formed that are at least partially disposed within the first substrate, that are spaced apart in a third direction, that extend in a fourth direction that is perpendicular to the third direction, and that partially enclose the first and second nanowires | 08-20-2009 |
20090258443 | Nonvolatile memory devices and methods of fabricating the same - Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member. | 10-15-2009 |
20100006849 | Thin Film Transistors - A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency. | 01-14-2010 |
20100013018 | CMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second transistor having a second conductivity type are positioned on the substrate, respectively. The first transistor includes a first gate positioned on a first surface of the channel material through a medium of a gate insulation layer and a pair of ohmic contacts positioned on a second surface of the channel material and crossing over both side portions of the first gate electrode, respectively. The second transistor includes a second gate positioned on the first surface of the channel material through a medium of the gate insulation layer and a pair of Schottky contacts positioned on the second surface of the channel material and crossing over both side portions of the second gate electrode, respectively. | 01-21-2010 |
20100314600 | Memory Units and Related Semiconductor Devices Including Nanowires - Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided. | 12-16-2010 |
20110007329 | Methods of inspecting structures - A method of inspecting a structure. The method includes preparing preliminary spectrums of reference diffraction intensities according to critical dimensions of reference structures, obtaining a linear spectrum from the preliminary spectrums in a set critical dimension range, radiating light to respective measurement structures formed on a substrate, measuring measurement diffraction intensities of the light diffracted by the measurement structures, and obtaining respective critical dimensions of the measurement structures from the measurement diffraction intensities using the linear spectrum. | 01-13-2011 |
20110263081 | METHODS OF MANUFACTURING CMOS TRANSISTOR - A method of manufacturing a CMOS transistor can be provided by forming first and second gate electrodes on a substrate and forming a gate insulation layer on the first and second gate electrodes. A semiconductor channel material having a first conductivity type can be formed on the gate insulation layer. A pair of ohmic contacts can be formed on the semiconductor channel material such that the ohmic contacts cross over both side portions of the first gate electrode, respectively. A pair of Schottky contacts can be formed on the semiconductor channel material such that the Schottky contacts cross over both side portions of the second gate electrode, respectively. | 10-27-2011 |
20110294268 | Thin Film Transistors and Methods of Manufacturing Thin Film Transistors - A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency. | 12-01-2011 |