Patent application number | Description | Published |
20120288782 | STABLE ULTRALYOPHOBIC COATING FOR PEMFC BIPOLAR PLATE WATER MANAGEMENT - An electrode plate is disclosed. The electrode plate includes a plate having an active area, a feed region in fluid communication with the active region, and a tunnel region in fluid communication with the feed region and a manifold region, an ultralyophobic coating on one or more of at least a portion of the tunnel region, at least a portion of the feed region, and an interface between the tunnel region and the manifold region. Fuel cells using the electrode plate and methods of making electrode plates are also described. | 11-15-2012 |
20130122390 | METHOD OF CONTROLLING THICKNESS OF FORM-IN-PLACE SEALING FOR PEM FUEL CELL STACKS - A sealed assembly is made using sealant including a deformable spacer to control thickness without adversely impacting elasticity and sealing force. Deformable spacers (e.g., elastomer, polyolefin, etc.) are mixed with an elastomeric precursor material and dispensed onto an assembly component, such as a fuel cell bipolar plate, and the remaining component(s) are assembled by pressing against the deformable spacer to ensure a defined seal thickness. The precursor is cured to form a seal that is further compressed to provide an effective sealing force. The deformable spacers control the thickness of a sealed area and allow use of form-in-place sealing processes. | 05-16-2013 |
20130331509 | Flexible, Low Temperature, Filled Composite Material Compositions, Coatings, and Methods - There is provided a flexible, low temperature, filled composite material composition and method of synthesizing the composite material composition. The composite material composition has a segmented copolymer elastomer having an α,ω-(alpha, omega)-dihydroxy terminated polysiloxane species, a diisocyanate species, and an amine or hydroxy terminated chain extender. The composite material composition further has a solid particulate filler. The composite material composition has a high flexibility at a temperature of down to about −100 degrees Celsius, has a percent elongation of greater than about 100%, and has a tensile strength of greater than about 5 MPa (megapascals). | 12-12-2013 |
20140162022 | STRUCTURAL COATINGS WITH DEWETTING AND ANTI-ICING PROPERTIES, AND COATING PRECURSORS FOR FABRICATING SAME - Variations of this invention provide durable, impact-resistant structural coatings that have both dewetting and anti-icing properties. The coatings in some embodiments possess a self-similar structure that combines a low-cost matrix with two feature sizes that are tuned to affect the wetting of water and freezing of water on the surface. Dewetting and anti-icing performance is simultaneously achieved in a structural coating comprising multiple layers, wherein each layer includes (a) a continuous matrix; (b) discrete templates dispersed that promote surface roughness to inhibit wetting of water; and (c) nanoparticles that inhibit heterogeneous nucleation of water. These structural coatings utilize low-cost, lightweight, and environmentally benign materials that can be rapidly sprayed over large areas using convenient coating processes. The presence of multiple layers means that if the surface is damaged during use, freshly exposed surface will expose a coating identical to that which was removed, for extended lifetime. | 06-12-2014 |
20140272301 | STRUCTURAL COATINGS WITH DEWETTING AND ANTI-ICING PROPERTIES, AND PROCESSES FOR FABRICATING THESE COATINGS - Durable, impact-resistant structural coatings with dewetting and anti-icing properties are disclosed. The coatings possess a self-similar structure with two feature sizes that are tuned to affect the wetting of water and freezing of water on the surface. Dewetting and anti-icing performance is simultaneously achieved in a structural coating comprising multiple layers, with each layer including (a) a continuous matrix; (b) porous voids, dispersed within the matrix, to inhibit wetting of water; and (c) nanoparticles, on pore surfaces, that inhibit heterogeneous nucleation of water. These structural coatings utilize low-cost and lightweight materials that can be rapidly sprayed over large areas. If the surface is damaged during use, fresh material will expose a coating surface that is identical to that which was removed, for extended lifetime. | 09-18-2014 |
20140329166 | METHOD OF CONTROLLING THICKNESS OF FORM-IN-PLACE SEALING FOR PEM FUEL CELL STACKS - A sealed assembly is made using sealant including a deformable spacer to control thickness without adversely impacting elasticity and sealing force. Deformable spacers (e.g., elastomer, polyolefin, etc.) are mixed with an elastomeric precursor material and dispensed onto an assembly component, such as a fuel cell bipolar plate, and the remaining component(s) are assembled by pressing against the deformable spacer to ensure a defined seal thickness. The precursor is cured to form a seal that is further compressed to provide an effective sealing force. The deformable spacers control the thickness of a sealed area and allow use of form-in-place sealing processes. | 11-06-2014 |
20150044420 | Coatings, Coating Compositions, and Methods of Delaying Ice Formation - A coating includes at least one coating layer containing first particles, second particles, and third particles distributed throughout a cross-linked, continuous polymer matrix. An outer surface of the coating layer includes surfaces of at least first particles extending outward from a top periphery of the polymer matrix. The outer surface exhibits a property of delaying ice formation compared to the coating layer without the first particles. A method includes applying a coating composition in one application step. The one-step coating composition contains first particles, second particles, and third particles in a base containing a polymer. A coating composition includes first particles, second particles, and third particles distributed in a matrix precursor. | 02-12-2015 |
20150133602 | LOW TEMPERATURE SEGMENTED COPOLYMER COMPOSITIONS AND METHODS - There is provided a method of synthesizing a segmented copolymer that includes mixing one or more α,ω (alpha, omega) amine or α,ω (alpha, omega) hydroxyl terminated polysiloxane first soft segments having an average molecular weight of between about 2500 grams per mole to about 10,000 grams per mole, and one or more diisocyanate species, together to form a first reaction product; mixing the first reaction product and one or more low molecular weight diol or diamine chain extenders each having an average molecular weight of less than 400 grams per mole, together in a solvent to form a segmented copolymer; and, removing the solvent. | 05-14-2015 |
20150152215 | FORMULATIONS, METHODS, AND APPARATUS FOR REMOTE TRIGGERING OF FRONTALLY CURED POLYMERS - In some variations, the invention provides a curable adhesive formulation comprising a curable liquid precursor capable of frontal polymerization, wherein the liquid precursor comprises a monomer and a polymerization catalyst, and frontal-polymerization-triggering susceptors in contact with, or contained within, the liquid precursor. The susceptors may include conducting and/or magnetic solid particles capable of induction heating in the presence of a remotely applied electromagnetic field. Other variations provide a polymer-curing system comprising a curable liquid precursor, frontal-polymerization-triggering susceptors, and an apparatus configured to remotely produce an alternating electromagnetic field in line-of-sight with the susceptors (but not necessarily in line-of-sight with the liquid precursor), thereby generating induction heating to initiate the frontal polymerization. The susceptors may be about 0.1 wt % to about 50 wt % of the curable formulation. Other variations provide a method of curing an adhesive joint through an opaque barrier. | 06-04-2015 |
20150158969 | POLYSULFIDE AND POLYFLUOROETHER COPOLYMER COMPOSITIONS - Novel segmented polysulfide-polyfluoroether copolymers are disclosed. In particular, a polyurethane segmented copolymer composition is provided, comprising one or more polyurethane/urea hard segments, one or more polysulfide soft segments, one or more polyfluoroether soft segments, isocyanate species or derivatives thereof contained in each of the segments, and one or more curatives. The polysulfide soft segments and the polyfluoroether soft segments are together about 50 wt % to about 95 wt % of the copolymer. The weight ratio of the polysulfide soft segments to the polyfluoroether soft segments is from about 0.1 to about 10. The polyfluoroether soft segments are characterized by a glass-transition temperature of about −85° C. or lower. These copolymers are useful in elastomers for improved fluid resistance, substrate adhesion, and low-temperature flexibility. These properties are desirable for sealants and other applications. | 06-11-2015 |
Patent application number | Description | Published |
20090174015 | Memory Cell and Method of Forming a Magnetic Tunnel Junction (MTJ) of a Memory Cell - A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane. | 07-09-2009 |
20110051509 | System and Method to Manufacture Magnetic Random Access Memory - A system and method to manufacture magnetic random access memory is disclosed. In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer into a source line having a substantially rectilinear portion. The method also includes coupling the source line, at the substantially rectilinear portion, to a first transistor using a first via. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction device. The method includes coupling the source line to a second transistor using a second via, where the second transistor is configured to supply a second current received from the source line to a second magnetic tunnel junction device. | 03-03-2011 |
20110068433 | FORMING RADIO FREQUENCY INTEGRATED CIRCUITS - Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate. | 03-24-2011 |
20110084358 | Apparatus and Method for Through Silicon via Impedance Matching - Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit. | 04-14-2011 |
20110316657 | Three Dimensional Wire Bond Inductor and Transformer - A three-dimensional inductor or transformer for an electronic packaging system that includes a plurality of conductive traces and a plurality of conductive wire bonds. The traces are located in a single layer, and each have a first and second pad. Each of the wire bonds couples the second pad of one trace to the first pad of another trace. The trace and wire bonds create a continuous conductive path from the first pad of a first trace to the second pad of a last trace. Passing a current from the first trace to the last trace creates an electromagnetic field between the single layer and the wire bonds. The transformer includes two independent and electromagnetically coupled inductors that can be interleaved. The continuous conductive path can be solenoid-shaped. A shielding layer can also be included that blocks the substrate from the electromagnetic field of the inductor or transformer. | 12-29-2011 |
20130095576 | TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION - Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor. | 04-18-2013 |
20130119494 | MTJ STRUCTURE AND INTEGRATION SCHEME - A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack. | 05-16-2013 |
20130297981 | LOW COST HIGH THROUGHPUT TSV/MICROBUMP PROBE - A first apparatus, such as a die or a semiconductor package, has signal paths extending through the apparatus. The signal paths can include through vias and other components. The signal paths are operable to communicate with a second apparatus when the second apparatus is stacked with the first apparatus. The first apparatus also has pass gates. Each pass gate is configurable in response to a signal, to short a pair of the signal paths to enable substantially simultaneous testing of the signal paths. The pass gates may be configurable to isolate the signal paths during operation of the first apparatus. | 11-07-2013 |
20140010006 | NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION - A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ. | 01-09-2014 |
20140063922 | MRAM WORD LINE POWER CONTROL SCHEME - Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated, with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro. | 03-06-2014 |
20140131549 | THROUGH SILICON OPTICAL INTERCONNECTS - Some implementations provide a semiconductor device that includes a first die and an optical receiver. The first die includes a back side layer having a thickness that is sufficiently thin to allow an optical signal to traverse through the back side layer. The optical receiver is configured to receive several optical signals through the back side layer of the first die. In some implementations, each optical signal originates from a corresponding optical emitter coupled to a second die. In some implementations, the back side layer is a die substrate. In some implementations, the optical signal traverses a substrate portion of the back side layer. The first die further includes an active layer. The optical receiver is part of the active layer. In some implementations, the semiconductor device includes a second die that includes an optical emitter. The second die coupled to the back side of the first die. | 05-15-2014 |
20140167273 | LOW PARASITIC PACKAGE SUBSTRATE HAVING EMBEDDED PASSIVE SUBSTRATE DISCRETE COMPONENTS AND METHOD FOR MAKING SAME - One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer. | 06-19-2014 |
20140197902 | DIPLEXER DESIGN USING THROUGH GLASS VIA TECHNOLOGY - A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate. | 07-17-2014 |
20140264331 | DAISY CHAIN CONNECTION FOR TESTING CONTINUITY IN A SEMICONDUCTOR DIE - An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch. | 09-18-2014 |
20140268615 | TWO-STAGE POWER DELIVERY ARCHITECTURE - A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator. | 09-18-2014 |
20140327496 | TUNABLE DIPLEXERS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DIC) AND RELATED COMPONENTS AND METHODS - Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used. | 11-06-2014 |
20140354372 | SYSTEMS FOR REDUCING MAGNETIC COUPLING IN INTEGRATED CIRCUITS (ICS), AND RELATED COMPONENTS AND METHODS - Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter. | 12-04-2014 |
20150035162 | INDUCTIVE DEVICE THAT INCLUDES CONDUCTIVE VIA AND METAL LAYER - An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer contacts a conductive via that extends at least partially within the substrate. The metal layer and the conductive via form at least a portion of an inductive device. | 02-05-2015 |
Patent application number | Description | Published |
20100077244 | LOW POWER ELECTRONIC SYSTEM ARCHITECTURE USING NON-VOLATILE MAGNETIC MEMORY - A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit. | 03-25-2010 |
20100308435 | Through Silicon Via With Embedded Decoupling Capacitor - A semiconductor die, having a substrate, includes a through silicon via. The through silicon via includes a decoupling capacitor having a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor. The decoupling capacitor is configured to provide local charge storage for components on the semiconductor die. | 12-09-2010 |
20110035529 | Partitioning a Crossbar Interconnect in a Multi-Channel Memory System - A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters. | 02-10-2011 |
20110087846 | Accessing a Multi-Channel Memory System Having Non-Uniform Page Sizes - A method includes predicting a memory access pattern of each master of a plurality of masters. The plurality of masters can access a multi-channel memory via a crossbar interconnect, where the multi-channel memory has a plurality of banks The method includes identifying a page size associated with each bank of the plurality of banks The method also includes assigning at least one bank of the plurality of banks to each master of the plurality of masters based on the memory access pattern of each master. | 04-14-2011 |
20110193212 | Systems and Methods Providing Arrangements of Vias - A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values. | 08-11-2011 |
20110233718 | Heterogeneous Technology Integration - A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump. | 09-29-2011 |
20110234357 | Three Dimensional Inductor and Transformer Design Methodology of Glass Technology - An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path. | 09-29-2011 |
20110273926 | Method and Apparatus of Probabilistic Programming Multi-Level Memory in Cluster States Of Bi-Stable Elements - A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data. | 11-10-2011 |
20110320698 | Multi-Channel Multi-Port Memory - A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels. | 12-29-2011 |
20110320751 | Dynamic Interleaving Of Multi-Channel Memory - In a particular embodiment, a dynamic interleaving system changes the number of interleaving channels of a multi-channel memory based on a detected level of bandwidth requests from a plurality of master ports to a plurality of slave ports. At a low level of bandwidth requests, the number of interleaving channels is reduced. | 12-29-2011 |
20120033490 | Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction - A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. | 02-09-2012 |
20120199949 | High Density Metal-Insulator-Metal Trench Capacitor - Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition. | 08-09-2012 |
20130040436 | THROUGH SUBSTRATE VIA WITH EMBEDDED DECOUPLING CAPACITOR - A method of manufacturing a semiconductor die having a substrate with a front side and a back side includes fabricating openings for through substrate vias on the front side of the semiconductor die. The method also includes depositing a first conductor in the through substrate vias, depositing a dielectric on the first conductor and depositing a second conductor on the dielectric. The method further includes depositing a protective insulator layer on the back side of the substrate covering the through substrate vias. | 02-14-2013 |
20130222060 | MUTUALLY COUPLED MATCHING NETWORK - An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit. | 08-29-2013 |
20140043756 | ACTIVE THERMAL CONTROL FOR STACKED IC DEVICES - Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired. | 02-13-2014 |
20140098602 | METHOD AND APPARATUS OF PROBABILISTIC PROGRAMMING MULTI-LEVEL MEMORY IN CLUSTER STATES OF BI-STABLE ELEMENTS - A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data. | 04-10-2014 |
20140111064 | COMPOSITE DILATION MODE RESONATORS - This disclosure provides systems, methods and apparatus related to acoustic resonators that include composite transduction layers for enabling selective tuning of one or more acoustic or electromechanical properties. In one aspect, a resonator structure includes one or more first electrodes, one or more second electrodes, and a transduction layer arranged between the first and second electrodes. The transduction layer includes a plurality of constituent layers. In some implementations, the constituent layers include one or more first piezoelectric layers and one or more second piezoelectric layers. The transduction layer is configured to, responsive to signals provided to the first and second electrodes, provide at least a first mode of vibration of the transduction layer with a displacement component along the z axis and at least a second mode of vibration of the transduction layer with a displacement component along the plane of the x axis and they axis. | 04-24-2014 |
20140206105 | TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION - Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor. | 07-24-2014 |
20140354378 | DESIGN FOR HIGH PASS FILTERS AND LOW PASS FILTERS USING THROUGH GLASS VIA TECHNOLOGY - A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution. | 12-04-2014 |
20150056722 | MTJ STRUCTURE AND INTEGRATION SCHEME - A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack. | 02-26-2015 |
20150070979 | PHYSICALLY UNCLONABLE FUNCTION BASED ON PROGRAMMING VOLTAGE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY - One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage. | 03-12-2015 |
20150071430 | PHYSICALLY UNCLONABLE FUNCTION BASED ON THE INITIAL LOGICAL STATE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY - One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array. | 03-12-2015 |
20150071431 | PHYSICALLY UNCLONABLE FUNCTION BASED ON THE RANDOM LOGICAL STATE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY - One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state. | 03-12-2015 |
20150071432 | PHYSICALLY UNCLONABLE FUNCTION BASED ON RESISTIVITY OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY MAGNETIC TUNNEL JUNCTIONS - One feature pertains to least one physically unclonable function based on an array of magnetoresistive random-access memory (MRAM) cells. A challenge to the array of MRAM cells may identify some of the cells to be used for the physically unclonable function. Each MRAM cell may include a plurality of magnetic tunnel junctions (MTJs), where the MTJs may exhibit distinct resistances due to manufacturing or fabrication variations. A response to the challenge may be obtained for each cell by using the resistance(s) of one or both of the MTJs for a cell to obtain a value that serves as the response for that cell. The responses for a plurality of cells may be at least partially mapped to provide a unique identifier for the array. The responses generated from the array of cells may serve as a physically unclonable function that may be used to uniquely identify an electronic device. | 03-12-2015 |
20150074433 | PHYSICALLY UNCLONABLE FUNCTION BASED ON BREAKDOWN VOLTAGE OF METAL- INSULATOR-METAL DEVICE - One feature pertains to a method of implementing a physically unclonable function that includes providing an array of metal-insulator-metal (MIM) devices, where the MIM devices are configured to represent a first resistance state or a second resistance state and a plurality of the MIM devices are initially at the first resistance state. The MIM devices have a random breakdown voltage that is greater than a first voltage and less than a second voltage, where the breakdown voltage represents a voltage that causes the MIM devices to transition from the first resistance state to the second resistance state. The method further includes applying a signal line voltage to the MIM devices to cause a portion of the MIM devices to randomly breakdown and transition from the first resistance state to the second resistance state, the signal line voltage greater than the first voltage and less than the second voltage. | 03-12-2015 |
20150092314 | CONNECTOR PLACEMENT FOR A SUBSTRATE INTEGRATED WITH A TOROIDAL INDUCTOR - A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector. | 04-02-2015 |